| 8.00 - 9.00 |
Registration |
| 9.00 - 9.45 |
Introduction
IP Market Status", Prof. G. Saucier, INPG,
Design&Reuse, France |
| 9.45 - 10.00 |
Coffee Break |
| 10.00 - 10.40 |
Session 1 : "Object Oriented IP Modelling and Data Base"
Session
Chair : A. Betts, STMicroelectronics, France |
| 10.00 - 10.20 |
"Object Oriented Hardware Modeling and Simulation Based on Java",
T.
Kuhn, W. Rosenstiel, U. Kebschull, Univ. of Tubingen, Univ. Karlsruhe,
Germany |
| 10.20 - 10.40 |
"An Object-Oriented Management System Based on IP Key Attributes",
P.
Coeurdevey, R. Rafidinitrimo, G. Saucier, Design & Reuse, France |
| 10.40 -11.00 |
Coffee Break |
| 11.00 - 11.40 |
Session 2 ; "IP Protection "
Session Chair : U. Schlichtman,
Siemens, Germany |
| 11.00 - 11.20 |
"Intellectual Property Protection Via Hierarchical Watermarking",
E.
Charbon, I. Torunoglu, Cadence Design Systems, USA |
| 11.20 - 11.40 |
"Anatomy of a Protected Model",
S. Carlson, T. Hopes, Escalade,
ARM, USA |
| 11.40 - 13.00 |
Lunch |
| 13.00 - 14.20 |
Session 3 : " IP - Based System Design "
Session Chair :
Prof. G. De-Micheli, Stanford University, USA |
| 13.00 - 13.20 |
"Scalable Intellectual Properties for Design Reuse",
P.-X.
Thomas, A. Pirson, F. Yassa, Synopsys, USA |
| 13.20 - 13.40 |
"Effective Virtual Components for Synthesis",
Y. Fritzsch,
W. Ecker, U. Schlichtmann, Siemens, Germany |
| 13.40 - 14.00 |
"A Design Style to simplify IP Integration and Verification",
R. Foster, VLSI Technology, Germany |
| 14.00 - 14.20 |
"Design of reusable modules for high level designs",
A. Reutter,
B. Mosner, W. Rosenstiel, Robert Bosch GmbH, Univ. of Tuebingen, Germany |
| 14.20 - 14.40 |
Coffee Break |
| 14.40 - 16.00 |
Session 4 : " IP- Based System Design II"
Session Chair :
A. Greenhill, ARM, UK |
| 14.40 - 15.00 |
"IP-based design with WARELETs",
G. Gorla, Italtel, Italy |
| 15.00 - 15.20 |
"Encoding of Pointers for Hardware Synthesis",
L. Semeria,
G. De Micheli, Stanford University, USA |
| 15.20 - 15.40 |
"IP Reuse: A Novel VHDL to Verilog Translation Flow",
A.
Fasan, A. Fedeli, STMicroelectronics, USA, Italy |
| 15.40 - 16.00 |
"Modular Process Technologies for Efficient System Level Integration",
A. Sikora, NEC Electronics, Germany |
| 16.00 - 16.20 |
Coffee Break |
| 16.20 - 18.00 |
Panel : "IP Provider and ASIC Vendor Perspectives" Moderator:
Prof. G. Saucier, Design&Reuse, France
Panelists: P. Bricaud, Mentor Graphics, France
I. Jackson, LSI Logic,
USA A. Greenhill, ARM, United Kingdom
P. Delforge, Alcatel Microelectronics, Belgium
Poster Presentations:
"A New tool for Path Performance Optimization : POPS", S.
Cremoux, N. Azemard, M. Aline, D. Auvergne, LIRMM, France
"IP-Based Logic Synthesis Approach Targeting XILINX4000 Implementation",
I.Lemberski, Riga Aviation University, Latvia
"An Attribute Grammar Based Interactive High-Level Synthesis",
G. E. Economakos, I. Poulakis, G. Papakonstantinou, P. Tsanakas, National
Technical University of Athens, Greece
|
| 18.00 - 19.00 |
Design&Reuse User's Group Meeting (Opened to all registered members of Design&Reuse |
| 19.00 |
Banquet |
|
| 8.30 - 9.30 |
Session 5 : "IP Validation "
Session Chair : Prof. T. Ambler
University of Texas at Austin, USA |
| 8.30 - 8.50 |
"HW/SW Interface Validation in IP based System Design",
M.
O'Nils, A. Jantsch, Royal Institute of Technology, Sweden |
| 8.50 - 9.10 |
"What About Formal Verification of IP-based SoC Designs?",
A. E. K. Dekdouk, O. Ait-Mohamed, M. S. Jahan, E. Cerny, University of
Montreal, Canada |
| 9.10 - 9.30 |
"Hierarchy-Based Partitioning for IP Prototyping",
H. Krupnova,
C. Rabedaoro, A. Abbara, G. Saucier, INPG, France |
| 9.30- 9.50 |
Coffee Break |
| 9.50 - 10.50 |
Session 6 : "IP Prize Candidates Presentation"
Session Chair
: J.F. Agaesse Thomson TCS, France |
| 9.50 - 10.10 |
"The Embedded Microcontroller ASIC",
P. Ainsley, Mitel Semiconductor,
UK |
| 10.10 - 10.30 |
"Design of an ARM based System-on-a-Chip for Pay Phones",
J. Riesco, J. C. Diaz, Telefonica, Spain |
| 10.30 - 10.50 |
"IP Based Synthesis",
P. Cochennec, M. Johnson, P. Monnier,
STMicroelectronics, USA, France |
| 10.50 - 11.10 |
Coffee Break |
| 11.10 - 11.30 |
Special Session on Relations with Other Events SASIMI'98 Presentation,
Prof. M. Imai, Osaka University, Japan |
| 11.30 - 13.00 |
Lunch |
| 13.00 - 14.40 |
Session 7 : "IP Prize Candidates Presentation"
Session Chair
: P. Bricaud, Mentor Graphics, France |
| 13.00 - 13.20 |
"A VHDL Model of a Parameterizable CAN Controller as an Example
of a Reuse Library Component",
H. Braisz, N. Schumann, W. Glauert,
University of Erlangen-Nuremberg, Germany |
| 13.20 - 13.40 |
"Toward behavioural level IPs : high level synthesis of the Viterbi
algorithm",
C. Jego, E. Casseau, E. Martin, UBS University, France |
| 13.40 - 14.00 |
"Design of an IP-Based Modular Architecture for an MPEG-2 Video
Decoding Circuit",
L. Petit, J.-D. Legat, UCL Microelectronics Laboratory,
Belgium |
| 14.00 - 14.20 |
"PDF: Programmable Digital Filter IP Core",
L. Torres, M.
Robert, S. Colancon, M. Paindavoine, University of Bourgogne, France |
| 14.20 - 14.40 |
"CAM Macro Cells with Minimum Distance Detector using Time-Domain
Technique",
M. Ikeda, K. Asada, University of Tokyo, Japan |
| 14.40 - 14.50 |
Coffee Break |
| 14.50 - 16.50 |
Session 8 : "Hard IP and Macro Blocks Design"
Session Chair
: H. N. Nguyen, BULL, France |
| 14.50 - 16.50 |
"Building the Bridge Between EDA and Manufacturing - Re-Use of
IP",
H. van der Wildt, Sagantec, USA |
| 15.10 - 15.30 |
"Analysis and Optimisation of a Hard IP Migration Flow",
L. Couder, R. Leveugle, G. Saucier, INPG, France |
| 15.30 - 15.50 |
"A High Speed Completion Prediction Adder Based on Binary Carry
Lookahead Adder",
R. Zheng, K. Asada, University of Tokyo, Japan |
| 15.50 - 16.10 |
"Application of Piece Wise Linear Delay Representation to Macrocell
Characterisation",
M. Rezzoug, D. Auvergne, LIRMM, France |
| 16.10 - 16.30 |
"A Web-based Arithmetic Module Generator for High Performance
VLSI Applications",
J. Phil, J.-E. Oye, Norvegian University of Science
and Technology, Norvege |
| 16.30 - 16.50 |
"Reuse and Customisation of Parallel Prefix Adders",
V. Tchoumatchenko,
A. Guyot, T. Vassileva, INPG, France |
| 16.50 - 17.00 |
Best IP Prize Delivery by Press Representative |
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