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New Silicon IP
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Upgraded PUF-based Crypto Coprocessor (Compliant with TLS 1.3 / FIPS 186-5)
- PUF-based Hardware Root of Trust (Riscure Common Criteria Certified)
- Comprehensive Crypto Engine (NIST CAVP Certified)
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AES IP Core
- supports encryption and decryption
- supports 128, 192, and 256-bit key lengths
- has masked and non-masked modes
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VESA VDC-M V1.2 Decoder
- VESA VDC-M 1.2 Compliance
- Advanced Encoding Mechanisms
- Configurable High Resolution Support
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AI Processor Accelerator
- OPTIMIZED COMPUTATION - >80% Utilization
- LOW MEMORY - 16X Reduced
- SPEED - 10-30x Lower Clock Cycles
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MIPI M-PHY HS-G4 IP (M-PHY v4.1) in TSMC 40G
- Supports M-PHY HS-G4 and is available in TSMC 40G and other nodes
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Low Dropout (LDO) Capless Regulator, 25mA output, GF 22FDX
- Input voltage of 1.2V
- Output voltage of 0.79V to 0.86V
- Up to 25mA output current.
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PCIe 5.0 PHY for SF5
- Physical Coding Sublayer (PCS) block with PIPE interface
- Support PCIe 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
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NPU IP family for generative and classic AI with highest power efficiency, scalable and future proof
- Support wide range of activations & weights data types, from 32-bit Floating Point down to 2-bit Binary Neural Networks (BNN)
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Integrated Secure Element (iSE) for high-end devices with HW isolated secure processing
- Easy to integrate
- Tunable solution
- Fully digital
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VESA VDC-M V1.2 Encoder
- Superior video quality with efficient bandwidth utilization.
- Adaptable to a wide range of industry applications.
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8bits, 200Msps Sub-Ranging Flash AD Converter
- 8bits, 200MSPS Subranging AD Converter
- 0.18um Technology
- Supply 1.8V
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Secure Boot Hardware Engine
- Ensures integrity and authenticity of boot image
- Prevents any firmware down-grade (anti-rollback)
Top Silicon IP
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1
RISC-V-based AI IP development for enhanced training and inference
- Silicon-proven solutions tailored for AI workload optimization.
- Energy-efficient performance with industry-leading Perf/W.
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2
Synopsys 1.6T Ethernet MAC IP
- Supports all required features of the IEEE 802.3 specification
- Supports IEEE-managed objects, IETF MIB-II and RMON for management applications
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3
FlexNoC 5 Network-on-Chip (NoC)
- Physical Awareness for faster timing closure
- Higher margins
- Fewer wires
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4
DL-based Video Super Resolution Hardware IP
- In-house AI models
- Hardware IP
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Bluetooth Dual Mode v5.4 / IEEE 15.4 PHY/RF IP in TSMC22nm ULP
- Bluetooth 5.2 Dual-Mode radio, including EDR and LE 2Mbps for current and for next-generation BT high-quality audio streaming.
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UCIe PHY & D2D Adapter
- 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
- UCIe v1.1 specification
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Ncore 3 Coherent Network-on-Chip (NoC)
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11
Slave side SPI/QPI controller 133MHZ
- SPI
- QPI (Quad I/O SPI)
- 133MHz
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Ultra low power AI inference accelerator
- Energy Efficient
- High Performance
- Small footprint
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