AMBA Interface IP
Today’s advanced mobile applications place a lot of stress on the memory interface. The number of processing units in the system is growing and the communication protocols are being refined to handle the needs of those masters. Memory vendors are developing new devices and interfaces that enable data to be moved in and out of the memory systems at higher bandwidths. Servicing these needs demands a memory interface solution that combines high performance and low power. It must effectively connect the on-chip bus interconnect – AMBA - with the commodity off-chip DDR & LPDDR (Mobile DDR) SDRAM devices.
To address these requirements ARM provides everything you need to interface AMBA3 AXI systems with a broad ranges of dynamic memory solutions including Mobile DDR: the configurable PL340 Dynamic Memory Controller and the robust Velocity DDR PHY.
Each application will have unique requirements for throughput and power. A highly configurable solution such as the PL340 enables the designer to get maximum performance without compromising the power budget. The PL340 is synthesizable to a wide range of silicon processes and is designed to provide optimal throughput in systems with multiple AMBA3 AXI masters.
ARM Velocity® DDR family is a complete physical interface IP targeting double data rate SDRAM applications ranging from 200Mbps up to 1.6Gbps. It provides a reliable, robust physical interface between the memory controller and external SDRAM devices.
The Velocity DDR physical IP delivers a scalable memory interface that can be optimized to power, performance and area criteria.
When used in tandem the ARM controller and PHY solutions provide designers with the highest performance, highest quality AXI to MDDR connection.
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