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How to implement high-speed 667 Mbps DDR2 interfaces with FPGAs
By Seyi Verma, Altera
December 05, 2006
To achieve a robust high data rate, such as 667 Mbps in a DDR2 system, a dynamic auto-calibration PHY IP core significantly simplifies the memory interface design.
DDR2 is the second generation of double data rate (DDR) synchronous dynamic random access memory (SDRAM) capable of significantly higher data bandwidth. DDR2 improvements include lower power consumption, improved signal quality, and on-die termination schemes. Compared to the previous generation single data rate (SDR) SDRAM memories, DDR2 SDRAM memories transfer data on every edge of the clock, use the SSTL18 class II I/O standard with memories from up to 4 Gbits of data, and is widely available as modules such as dual in-line memory modules (DIMMs) or as components.
December 05, 2006
To achieve a robust high data rate, such as 667 Mbps in a DDR2 system, a dynamic auto-calibration PHY IP core significantly simplifies the memory interface design.
DDR2 is the second generation of double data rate (DDR) synchronous dynamic random access memory (SDRAM) capable of significantly higher data bandwidth. DDR2 improvements include lower power consumption, improved signal quality, and on-die termination schemes. Compared to the previous generation single data rate (SDR) SDRAM memories, DDR2 SDRAM memories transfer data on every edge of the clock, use the SSTL18 class II I/O standard with memories from up to 4 Gbits of data, and is widely available as modules such as dual in-line memory modules (DIMMs) or as components.
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