Multi-language Functional Verification Coverage for Multi-site Projects

By Apurva Kalia, Cadence Design Systems
February 18, 2008 -- edadesignline.com

This is Part 1 of a two parts article. The second part will be published early in March

Today's design paradigm is changing rapidly or to be more accurate it has already dramatically changed! Time to market pressures imply that most of today's SoC designs are re-use based derivative designs. This paradigm shift has created entirely new challenges for both design and verification teams, especially in the case of large projects that are developed throughout multiple sites. A significant part of the design cycle now involves managing and automating much of the SoC level integration that comes from the various sites. In order to address these issues we must first recognize the following:

IP blocks that form a part of the SoC could come from multiple sources spread over multiple geographies.
Different IP blocks may be written in various languages, making the SoC a multi-language design.
Each IP block carries its own verification IP so the overall verification environment may also be multi-language and distributed.

All this poses significant challenges for the overall verification effort. SoC integration teams must first ensure that they can verify the entire SoC in a timely manner, and ensure the highest quality of verification.

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