RTL synthesis can accelerate the entire implementation flow

Eyal Odiz, Synopsys
EE Times (03/31/2010 1:21 PM EDT)

You work in an environment where demanding design goals and aggressive project schedules go hand-in-hand with the push to get more complex products to market faster. And you have just finalized the RTL description of your company's next-generation product, a large system-on-chip (SoC). With just a few weeks remaining for final synthesis, place and route (P&R) and post-layout verification tasks, you wonder: can I still finish the job on schedule?

The answer depends on whether your synthesis solution is capable of delivering the best-possible quality-of-results (QoR) to meet all your timing, area, power and test requirements. Excellent QoR from synthesis is paramount to meeting your design objectives and cannot be compromised along the way. But given today's design challenges, this is a tall order. A robust synthesis solution must perform concurrent timing, area, power and test optimizations across multiple design corners and operating modes. To streamline the process, the synthesis engines can take advantage of the increased CPU parallelism now possible using inexpensive and widely-available multicore compute servers. Even so, your synthesis solution also must be able to accommodate a rich variety of design-for-test methodologies, low-power design techniques and a host of other design schemes that have emerged to meet the complex requirements of today's SoCs.

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