Powering Down: Enabling a Power Regression Flow for SoC Design

By Venkat Krishnaswamy, Calypto Design Systems
Embedded.com (05/03/10, 07:47:00 PM EDT)

Growing energy costs and the “green” revolution are driving designers to reduce the power consumption of SoCs used in today’s electronics systems. The most common method for optimizing power in these complex circuits is through clock gating.

Clocks that toggle unnecessarily are key contributors to dynamic power consumption in flip flops, related downstream logic, and in the clock network. Clock gating reduces dynamic power consumption by eliminating unnecessary clock toggling without affecting the functionality of the original design.

The goal of the designer, then, is to maximize the average clock-gating efficiency (CGE) of a design. CGE is defined as the percentage of time that registers in a design are clock-gated for a given stimulus or switching activity.

Maximizing CGE can be easier said than done. Designers may be able to make an “educated guess” about where to insert clock gating; however, once the register transfer level (RTL) modifications are made and RTL power analysis is run, the results may come back positive—power went down – or they may be negative—power remained largely unchanged or even increased after the changes.

Unfortunately, though, RTL power analysis tool results may not be very accurate. Precise analysis requires synthesizing the design and performing the power analysis at the gate level—a long and tedious process. In the often brief time allotted for power optimization during a project, design teams may only be able to complete one or two iterations, severely limiting power optimization.

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