SoCs: IP Reuse -> IP value depends on other occupants
IP value depends on other occupants
IP value depends on other occupants
By Mark-Eric Jones, Vice President, General Manager, Intellectual Property, MoSys Inc., Sunnyvale, Calif. , EE Times
March 21, 2000 (11:14 a.m. EST)
To realize the potential benefits of System-on-Chip (SoC) levels of integration requires design reuse on a massive scale-dozens, and ultimately hundreds, of blocks of intellectual property in multimillion-gate SoCs. As more and more IP blocks of various forms are used it will be important to understand the factors that affect the inherent value of different types.
One key factor determining the value of IP is the impact of the particular IP block on the resulting product compared to alternative approaches. This impact is normally reflected in improved functionality, better performance, lower power consumption, reduced cost or faster time-to-market. Although so-called commodity IP can often help achieve significant time-to-market benefits, it is what is called the star or differentiated IP that will deliver the greatest value in functionality, performance, power-consumption or cost. This differentiated IP is often protected by patents and of fers the user some unique characteristics that cannot be achieved with alternate technologies.
But this value is not just dependent on how differentiated the IP is; it is also a function of the type of IP. As we approach true SoC levels of integration, the key to the system's economics and performance lies more and more in the embedded memory that will occupy the lion's share of the die area, from 50 percent to 80 percent. Memory often limits the performance of the DSPs and processors that it serves. Although it is understandable that the choice of embedded microprocessor can have a large effect on the overall SoC performance, often it's the choice of the optimum memory technology that has the greatest impact on economics and performance. Indeed, given the large area occupied by memory, it is likely that in most cases the choice of embedded memory will have more effect than any other IP component of the SoC design.
A second key factor determining the value of IP is the number of times that it can be reused, spreading the value over multiple projects. The highest value IP will have a long life, being reused in a great variety of projects. But here we get into a new problem with IP blocks, such as memories or analog IP, that are inherently very dependent on the silicon process. The leading foundries are now introducing the next process geometry less than a year after the previous one. This rapid advancement into deeper and deeper submicron processes is delivering to SoC designers tremendous benefits in terms of these manufacturing capabilities. Each generation dramatically increases the number of gates that can be economically integrated into an IC, at the same time reducing operating power consumption and increasing the device speed. Designers are taking advantage of these rapidly improving capabilities, even when it means that each new product design is implemented in a new process generation.
Today this means that for significant reuse, IP must cross many process generations. One of the first questions prospective purchasers will ask an IP vendor is, "Is it silicon proven?" To manage development time scales and risks, project managers must ensure that their project is reusing (not just using) as much IP as possible that has already been silicon proven (preferably in volume production).
Logic synthesis from RTL or higher levels facilitates reuse of "soft" IP from one process generation to the next, so that a good return can be achieved on the initial investment in the design. In the case of RTL-based logic, reuse means that each implementation preserves the proven (normally complex) functionality of the building block. Considerable effort goes into establishing that the functionality is correct in all circumstances; by reusing the RTL the designer avoids having to repeat all that work. Given the high complexity of some soft IP blocks, this can represent considerable value to the designer needing to meet tough development budgets and time-to-market requirements. This value can be quantified not only in terms of the cost of saved effort, but-generally much more significantly-in terms of the advantages of bringing the product to market earlier. The key to the value of this soft IP is often encapsulated in the proven, complex functionality.
So what does reuse mean for other "hard" IP, such as memory or analog IP, when processes are changing so frequently? In the case of memory, the functionality is very simple compared to most soft IP and does not represent the primary value. The GDS2 physical-level implementation is tied to the short lifetime of a particular process and therefore also does not capture the full value of the IP. The key to the value of this memory IP is to look at the architectural level. The most significant value is associated with differentiated memory architecture if this architecture can carry across multiple process generations. But how does differentiation at the architectura l level translate into value?
First, differentiation at the architectural level can have much more impact on overall performance than at the detailed implementation level.
Typically, different detailed implementations may only differ by small percentages while different architectures can produce the revolutionary order-of-magnitude improvements that enable whole new products.
One example is MoSys' ultra-dense 1T-SRAM memory architecture. It achieves SRAM performance from the single-transistor bit cell that realizes less than a tenth of this performance in the traditional-architecture DRAM. The architecture has similarly dramatic effects on power consumption and density in addition to speed.
Second, the memory architecture-unlike the detailed physical implementation-endures across process generations, allowing more value to be realized through reuse. The current 1T-SRAM embedded memory designs for 0.18- and 0.15-micron processes reuse the MultiBank architecture-first used in Mo Sys' discrete memory products produced in 1995 using 0.6-micron process technology-with all the advantages of production experience of tens of millions of units in the meantime.
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