Expediting processor verification through testbench infrastructure reuse

Eric Hennenhoefer and Andrew Betts, Obsidian Software Inc.
EETimes (3/2/2011 8:59 AM EST )

Introduction

You might have thought that processor design was dying out, but think again. The architecture wars rage on between the majors, and plenty of smaller companies still find it worthwhile to develop proprietary architectures (or enhance existing ones) for niche markets. Although fundamental concepts in processor design evolve slowly, supporting technologies are advancing with great enthusiasm.

The growth of these supporting technologies is due, at least in part, to the sheer complexity and dynamics of industrial projects. Powerful algorithms and procedures, dealing with all common obstacles, are tried, tested and generally available. But even still, verification crises such as delayed signoff or even dead silicon are common.

61% of new processor designs require a re-spin [IC Insights 2009]
48% of total processor development cost are verification related [IC Economics, 2007]
55% of all processor designs are delivered late [IC Insights 2009]

This situation means that processor verification is still a major activity in the semiconductor industry, and that reliable and predictable processor verification outcomes remain important, if elusive goals. To reach these goals, the industry must make the inevitable shift toward embracing IP. Without prejudice to existing verification infrastructure, specialized processor verification IP can free engineers from historical development and maintenance commitments. This liberated time and energy can then allow a renewed focus on verification quality and turnaround times.

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