5 Wirebond Power Bus Watch Out!

Lee Wei Ling and Ang Boon Chong, Altera Corp

ABSTRACT

Wirebond package,lower cost package with lesser IO density always impose challenge for FPGA designer to meet the required power parameteric budget.This paper will share 5 watch outs on wirebond chip power bus planning.

1.0    Introduction

Wirebond power bus planning is always impose challenge to designer with the consideration of performance budget(supply voltage), mask cost and power pin count.

For FPGA wirebond power bus planning, core power bus take serious hit compare to IO periphery region for few reason, power pad is located at the edge of the chip, type of bump pad architecture implementation, power to signal IO ratio, metallization budget. IO periphery though have the advantage of closer to power pad placement advantage, however to tight IO drop budget on DDR3 performance is none trivial task either.

For this paper, it is to share the top 5 watch out for smoother wirebond power bus planning yet meeting the design performance,cost and power parameteric value. The discussion of this paper is based on traditional FPGA core wirebond power bus planning experience instead of new FPGA core full chip wirebond power bus planning methodology. However, the wirebond power bus watch outs is applicable regardless of the FPGA wirebond power bus planning methodology.

Due to design complexity, fab process, technology node,  and signoff PVT,some of the watch outs may not impact other wirebond power bus planner but do hope the reader may benefit from this sharing.

2.0    Traditional Wirebond Power Planning

For traditional wirebond power bus planning, it always a good start with guideline of 33% of the product level metallization (PD) is for core power bus as initial guideline (vccl_core+vss_core). It involved in series of discussion on various aspects as such

1. Metallization budget with various PD core signals taken into consider as well as dedicated power bus for selective IP placed within core region. Metallization planning from IO periphery region to reduce the IR drop from bump pad to core with consideration of IO periphery power and signal requirement
2. Power to Signal IO ratio with the requirement of various power pad taken into consideration as well as core power pad placement with feedback from packaging and technology group
3. BUMP Pad architecture where it is  2 tier or 3 tier as well as the bump pitch, bump pad width, the bump pad layer, 2 layer with bottom connected stack or 3 layer direct stack discussion with technology group
4. Floorplan aspect ratio which eventually dictate vertical or horizontal power bus density criticality to meet the required power parametric.
5. PDN(power distribution noise) vs performance of IP to decide the ideal power supply source for IP as well as whether the supply need to be separated, shorted on die, shorted on package or shorted on board decision.
6. Full chip thermal budget which limit the overall chip power budget. Wirebond package thermal budget will be the key limiting factor to power budget unlike flip-chip package thermal conductivity can be simply enhanced with better heatsink.
7. On die decap(ODC),on package decap(OPD) versus area impact due to AC power budget. For wirebond package device, it is typically much cost sensitive compare to flipchip package device. Hence, the higher AC power as well as performance requirement, will translate to higher decap required. At high frequency range, on board decap has negligible improvement impact to AC power noise.
8. Common ground rail or separated ground rail which eventually dictate the ground to IO ratio as well as IRDrop impact. Common ground rail does save improve the ground to IO ratio and at the cost of further IRDrop severeness due to the IO periphery drop impact.
9. PD power bus final review as layout slot and optimized the PD power bus across various IPs with appropriate IP signals taken into consideration for optimal metallization usage.
10. Last but not least, IP power definition signoff guideline and specifications with various IP owners and packaging team to ensure full chip power budget is meet and smooth power integration.

The aforementioned list are sample of power bus planning related only, excluding the power management task list.

3.0    Top 5 Wirebond Power Bus watch out

Watch_Out 1- unused IO pad sharing

For wirebond power bus, to achieve 70mV IR Drop, the overall resistance (die+package) allowed is only 9.625mOhm while the total resistance of a WB package ranges from 10.015mOhm to 13.39mOhm. Conventional solution is extra thick metallization is added to improve the resistance at the price of mask cost.

As the IO density of a WB package is less than that of an FC package, an IC die that supports both FC and WB package structures will have unbonded IOs when it is migrated from an FC package to a WB package as shown in figure 3.1

Figure 3.1: Watch_out_1 Unbonded IOs Due to Package Migration

By converting the unbonded IO to power pad through existing metallization,potential 20% IRDrop can be realize and meet the overall IRDrop budget. The metallization change is budgeted within the IO periphery region when migrating from flipchip package to wirebond package due to tighter performance required on DDR3 IO std. The converted IO pad is tapped to existing nearby supply pad ESD connection at zero cost mask solution.

Note from watch_out_1 is be resourceful on unused IO resources within die.

Watch_Out 2-high power density ip

For IP power bus selection, it is best to have consistent power density IPs group together within the same supply for even power distribution across chip. It ease the congestion of IR variation across chip besides the resistance impact.  Figure 3.2 below show the distribution of IPs power density(uW/um^2)

Figure 3.2: IP Power Density Distribution

From figure 3.2, it is obvious HIP IP is power hunger IPs compare to the rest.  

To validate the impact of power hungry to the IRDrop observed on Wirebond power bus, a testcase is conducted on single IP as equal power consumption with the rest of IPs in IRDrop&total power impact through graduate increment of the IP power ratio to the rest of IP. The result of this evaluation is as shown in figure 3.2a

Figure 3.2a: IP Power Density Impact

From figure 3.2a, it is observed that IRDrop has higher damage due to high power density IP compare to total power increment. The slop of IRDrop increment ratio due to the IP power density is none linear effect. However, the impact is also IP placement dependence.

Note from watch_out_2 is be alert of power hungry IP impact to wirebond power bus.

Watch_Out 3-slotted hole

During FPGA floorplan, it could be IO limited floorplan or core limited floorplan. For better area optimization, it is good practice to avoid IO limited floorplan for cost competitiveness. Hence, certain sensitive analog IP could be place within the core area which cause disruption to the core power bus contour.

From our FPGA power bus evaluation, smoothen core power bus will potentially improve the IRDrop by 7% per rail.

Figure 3.3 show the impact of slotted core power bus vs contour smoothen core power bus

 

Figure 3.3 Watch_Out_3 Power Bus Contour

Note from watch_out_3 is smoothen power bus contour is preferred for wirebond power bus robustness

Watch_Out 4-selective via

For FPGA PD layer power bus, power density per rail on each layer is not always evenly distributed due to the PD signal requirement. Power bus width at each layer is not guarantee to be consistent as well. Power bus at certain located may used as wire shield which need to be minimum width. Hence, the power bus resistant is not evenly distributed as a result. Due to the aforementioned reason, maximimum VIAing power wirebond power bus may worsen the power bus resistant due to the averaging effect of high resistance path.

For our FPGA design, the power bus density distribution is as such as shown in table 3.4

Table 3.4: Power Bus Density Per Layer

From our testcase, by selective VIAing solution which eliminates the high resistance, 21% IRDrop improvement is observed.

The selective VIAing solution deployed is as shown in figure 3.4

 

Figure 3.4: Watch_Out_4 Selective VIAing Solution

The implementation of selective VIAing solution is as shown in table 3.4a summary

Table 3.4a:Selective VIAing Summary

Note from watch_out_4 is though selective VIAing can improve the wirebond power bus robustness significantly without additional cost, do cautious of dangling power bus risk at verification stage

Watch_Out 5-Device Under Pad

For FPGA IO bank planning, leveling circuitry is placed in between IO sub bank.

For these 80um opening region, traditionally no pad is placed due to device sensitivity. Pending on characterization result, the placement of device under pad if feasible will help to mitigate the IRDrop impact.

Figure 3.5 illustrate the 80um opening region in IO bank.

 

Figure 3.5: Watch_Out_5 Device Under Pad

The result of PAD increment ratio for FPGA Design vs the Rail Drop Improvement Percentage in wirebond power bus planning is as shown in figure 3.5a

Figure 3.5a:Watch_Out_5 PAD Increment Ratio versus Rail Drop Improvement Percentage

From table 3.5, it is observed that the PAD increment ratio has none linear rail drop improvement which saturate at high PAD increment ratio.

Note from watch_out_5 is be resourceful on IO periphery opening region in wirebond power bus planning.

4.0    Summary

The summary of notes from 5 wirebond power bus watch out is as shown in table 4 below

 

Table 4: 5 Wirebond Power Bus Watch Out Summary

5.0    Acknowledgements

Thanks to Chris Lane for his valuable feedback and guidance on FPGA power management execution.Also thanks to Teik Wah for valuable inside on project execution.