Narayana Koduri, Atrenta Inc.
EETimes (7/23/2012 11:32 AM EDT)
With the plethora of mobile and consumer applications redefining the requirements for designing chips for low power requirements, designers have to be aware of power intent formats like Si2’s CPF (Common Power Format) and Accellera’s IEEE1801 UPF (Unified Power Format) to define and capture power intent for design implementation and verification. Designing and analyzing low power management in chip designs can best be accomplished at RTL, where designers adopt these formats to implement low power strategies like voltage and power islands. In this article, we will discuss several approaches on how these formats play a key role in capturing power intent for RTL design analysis and verification.
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