By Ron Wilson, Editor-in-Chief, Altera Corporation
Perhaps no semiconductor process has generated more controversy—before a single product has been shipped—than the 20 nm node. There was argument over whether the node would have to wait for production-ready EUV lithography. It did not: double-patterning, though expensive and restrictive on layout, has met the needs of the finest-resolution mask layers.
There were battles over whether the node would require finFET transistors. Intel, IBM, and UMC say yes; Samsung, TSMC, and GLOBALFOUNDRIES say no. TSMC has since equivocated a bit, pulling forward plans for a 16 nm finFET half-node. Perhaps most notoriously, NVIDIA CEO Jen-Hsun Huang publicly questioned the economic viability of the whole 20 nm node, saying that its cost per transistor might never drop below that of 28 nm.
Click here to read more ...