Angela Sutton, Synopsys
EETimes (11/29/2012 2:28 PM EST)
When your FPGA design fails to synthesize or fails to operate as expected on the board, the cause may not be obvious and the source of the failure may be hard to pinpoint among potentially thousands of RTL and constraint source files, many of which may have been authored by another designer. Given how lengthy FPGA design iterations and runtimes have become, designers need to find and root out what may be a large group of errors early in the design process and seek methods to focus the validation of the design on the board.
It is essential to apply smarter techniques to isolate specific errors under specific conditions, relate parts of the circuit that are behaving badly back to the source and apply the incremental fixes. You can save time by performing rudimentary design setup checks on clocks, constraints and module-level interfaces with a view to making your design specification good, before you waste hours in synthesis and place-and-route (P&R).
Synopsys Synplify Premier and Synplify Pro FPGA design tools and Identify RTL Debugger are among the products available to designers to handle these tasks. Such tools include features that enable designers to quickly isolate bugs and effectively reduce the length of runtimes and the number of iterations needed to bring up their boards.
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