Siddharth Guha & Kiran Vittal - Atrenta
EETimes (2/11/2013 7:00 AM EST)
While design sizes and complexities are increasing steadily, the power budget for electronic devices is aggressively decreasing. This increased demand for low power design is driven by various factors. First, wireless devices cannot afford high power consumption due to the limitations of battery power. Second, even wired devices cannot afford high power consumption as the cooling costs are significant. Additionally, in the last few years, government bodies, such as the European Union, have recognized the need for energy efficient devices and have set strict regulations. So various forces are now compelling the market to produce power-efficient electronic devices.
It is very important for system-on-a-chip (SoC) designers to understand power consumption early in the design cycle to meet the desired power budget. However, one of the complexities involved is that in the initial stages of SoC design not much information is available to accurately estimate power. As the design progresses, power consumption becomes clearer with the availability of simulation vectors, technology libraries and decisions taken for synthesis and routing. On the other hand, the best time to optimize power is in the early stages of the design. The later it gets in the design flow, the harder it gets to make changes to reduce power. One of the biggest challenges for the designer is to have a set of tools and flows which can work right from the very early stage of the design through the later stages in the flow. This article discusses some of the challenges of setting up such a flow and shares five guidelines for early and accurate power analysis at the register transfer level (RTL) of abstraction. The RTL abstraction for an SoC is developed during the early stages.
Click here to read more ...