Analyzing the Options in High-Bandwidth System Interconnect-or, Serial: It's Not Just for Breakfast

By Ron Wilson, Editor-in-Chief, Altera Corporation

Interconnect architecture within systems used to be so obvious. Physical constraints, such as chip boundaries and board edges, imposed a partitioning scheme on the system. And then standards, such as GPIB or USB for I/Os, and microprocessor buses for internal connections, defined the interconnect scheme. Beyond these standards, connections were usually asynchronous and point-to-point.

But today, the vast increase in bandwidth between subsystems, the risk of low-latency paths extending across subsystem boundaries, and tightening power and cost budgets have conspired to complicate everything. In many designs, it is not feasible to route a CPU bus—or even a peripheral bus—all around the system. Subsystems come as systems on chips (SoCs), bringing with them some chip designer’s preconception of your system’s interconnect architecture. And with low I/O voltages and tiny rise times, a point-to-point interconnect presents increased timing, signal-integrity, and board-design challenges.

Into this scenario of growing complexity has come another alternative. High-speed serial interconnect has been used primarily in the communications industry for carrying streams of packets over long distances. With advanced silicon process technology, the interfaces for these serial links have become small enough, and the data rates high enough, that multi-Gbps serial links are replacing parallel buses, and even asynchronous I/Os, in many systems.

A perhaps obvious example is PCI Express® (PCIe®). The original PCI was a fairly traditional parallel synchronous bus. As the personal computer’s bandwidth needs increased, Intel moved from this topology to multiple lanes of high-speed serial links. A similar evolution transformed the old AT Attachment bus for mass-storage devices into the now-familiar Serial ATA (SATA).

But the concept has application beyond peripheral buses. To understand why high-speed serial links are showing up in point-to-point connections even with the boundaries of a single board, we should take a look at some system partitioning issues.

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