Star Sung, Blue Lan, Jacques Baudier (TITC)
A display Driver with on-chip frame buffer and a scalable image compression codec reaching visually lossless image quality is presented. The frame buffer compression codec can encode and decode up to eight pixels in one clock cycle. Integrating a whole frame buffer with RGB=888 or 10-10-10 bits into the display driver sharply reduces power dissipated between the AP chip and Display board. The existing working chips are manufactured by both UMC and TSMC 55nm high voltage CMOS process. A new chip design with on-chip frame buffer SRAM includes a scalable compression ratio codec supporting HD720 (1280x720), Full-HD (1920x1080), (Max. 2560x1280) is completed which reduces the frame buffer SRAM density and area by a factor ranging from 2.0 times to 6.0 times and cuts the power consumption of the on-chip SRAM frame buffer by ~6.0 times of which 6 times is contributed by less capacitive bit line load. The 2X compression codec having 40K gates in encoder and 15K in decoder accepts both YUV and RGB color formats. A smart engine detects the Tx/Rx bandwidth availability and decides the compression ratio to avoid data congestion. The high image quality is achieved by applying patented proprietary compression algorithms including accurate prediction in DPCM, a new VLC coding with accurate predictive divider and an intelligent bit rate distribution control and an intelligent random truncation mechanism is realized to avoid artifact caused from error propagation.
The display device in old mobile phone system like the display panel with display timing control and display driver receives the image from the AP or system controller like VGA controller or a base-band controller chip. To avoid degradation of image quality due to the charge leakage, an inheritance of the display panel capacitance, the image to be displayed will be refreshed ~ 30 to 120 times per second which dissipates a lot of power due to the charging and discharging the large display panel capacitance as shown in Fig. 1
To reduce the power consumption of refreshing the image fames, an on-chip frame buffer comprising of semiconductor SRAM cell arrays which for example, in 55m high voltage process with HD720 resolution (1280x720) dominates about 60% die area making the cost of display driver chip, an LCD driver almost 40% higher in price than that of ram-less driver chip. Taiwan ImagingTek (TITC & TITC-USA), a world leading lossless compression IP supplier Magnachips, Novatek and Orise the leading LCD Driver IC suppliers have jointly worked in reducing the frame buffer SRAM die size in the LCD driver chip by frame buffer compression. Novatek and Orise together have shipped more than 100M HD720 resolution LCD Driver chips which shows visually no artifact under 2.0 times compression ratio. This project as shown in Fig. 2 results also in the power reduction by ~4.0 times which is contributed by 2 times less capacitive load and another 2 times from data rate reduction by the TITC technology of near lossless image compression. From Q3/2013, Novatek starts mass production by shipping LCD Driver chip with Full-HD (1920x1080, ~60M bits without compression) and TITC 2 times lossless image compression IP which reduces the die cost by a factor of ~40%.
Fig. 2 The LCD driver with T-CON and an on-chip frame buffer SRAM and a compression codec
2. FUNDAMENTALS AND IMAGE QUALITY UNDER COMPRESSION
Compression results in more or less image quality degradation unless the pure lossless algorithm which does not guaranty a minimum ratio of data reduction which is critical in determining the amount of the on-chip frame buffer SRAM. TITC has successfully developed compression algorithms and the corresponding VLSI macro-IP with fixed data rate or said compression ratio at near lossless image quality which from all tested still images shown visually lossless.
2.1 Innovative compression algorithms resulting in high image quality
A couple of compression algorithms have played the keys to such a good image quality, visually and in PSNR, including:
- Accurate prediction in DPCM as well as accurately stops the DPCM coding with prediction. The former making shorter code possible, while the later minimizing the code length to original code length. The later gains ~ 2dB.
- Golomb-Rice-like VLC coding: accurate predictive divider resulting in shorter code of Quotient. This VLC coding gains 2-3 dB better quality than the for the Golomb-Rice coding.
- Intelligent bit rate distribution: with accurate prediction, according to line to line correlation, an intelligent means of assigning bit rate to compress each segment of pixels reaches ~ 3dB increase in image quality.
Comparing to the international lossless compression standard called JPEG-Lossless, or said JPEG-LS, the TITC-LS is the same competitive in compression ratio as shown in Fig. 3 with much less hardware (gate count) and feasibility of scaling up to pursuing higher throughput in both compression and decompression.
Lena and Pepper are well known and commonly used in research community. While âDeskTopâ is very common and real display screen. WordRG has complex pattern of Green back ground with pink text in upper side and pink background green text which is believed to test worst case in Chroma. DogCats has 2/3 area of animal fur for high frequency testing in compression ration. The average of the five tested images of the JPEG-LS is 2.35X, while the TITC-LS reaches 2.43X compression ratio under lossless quality as shown in Table 1.
2.2 TITC-LS derivative compression algorithms with fixed compression ratio
Based on the efficient lossless compression principles, a couple of innovative algorithms of predicting divider value and bit rate distribution are applied to make the TITC fixed ratio compression mechanism reach high image quality. In implementing the compression codec with specific fixed bit rate, TITC codec receives the input pixels and compresses segment by segment with variable bit rate assigned to each segment based on the prediction to optimize the quality.
Table 2 lists the simulation results of the TITC compression. At 1.6X times ratio, only âPepperâ does not reach lossless quality, (61.39 dB), all others including Lena reach lossless quality. At 2.0X times compression ratio, DeskTop and WordRG reach lossless quality while DogCats is 60.89 dB, Lena is 50.97 dB and Pepper is 50.36 dB. While, under 3 times compression ratio, care has been taken to ensure that there is visually no artifact.
Due to the fact that the on-chip HD720 frame buffer without compression dominates ~50% die area (Full-HD frame buffer dominates 85% of LCD driver die area), higher compression ratio, like 4X and 6X with acceptable image and video quality is highly expected in new chip design. TITC decide to focus on 4 to 6 times compression ratio mainly for the following three factors:
- Marketing reason: Most smart phone vendors already using 2X times IP and highly expect 4X times compression ratio to reduce bandwidth and memory density in the on-chip Frame Buffer.
- Image quality: 3X times ration has visually no artifact even for the most complex still image pattern.
- Bandwidth: in principle, ideally, 3X times saves 3X times compared. In future 2560x1440 resolution, 4X and higher compression ratio becomes critical in most portable device.
Table 23. VLSI SPECIFICATIONS OF THE COMRPESSION CODEC
In VLSI implementation, to reach the same throughput of pixel number per clock or a fixed time, the JPEG-LS needs at least 40K logic, multiple lines of buffer equivalent to 350K bits for storing the context for the arithmetic coding. While, the gate count for the TITC-LS is 4K in encoder and 4K gates in decoder with potential scaling up for higher throughput, and this algorithm allows VLSI implementation of encoding and decoding more than 8 pixels or said one pixel per clock @300 MHz. The VLSI module for the 3x/4x times image compression used in this Full-HD panel LCD driver is comprised of the following technical specifications which including high throughput per clock and low gate count in both encoder and decoder resulting in easy integration and scaling. Encoder: 120K gates, Decoder: 50K gates plus 1 line buffer in both encoder and decoder. Under TSMC 55nm HV process, the encoder can run up to 300 MHz in typical process corner, and decoder runs 233MHz. Most LCD driver requires < 200MHz which results in the TITC compression Codec having capability of encoding up to 8 pixels and decoding 6 pixels in a single clock cycle of 250MHz. This kind of high efficiency compression codec makes random accessing feasible by quick recovering pixels in any location within a compression frame buffer. Another side effect of applying this compression codec is the result in power reduction by ~9.0 times is appreciated by most mobile phone system vendors.
4. SCALABLE IMAGE COMPRESSION FOR VIDEO APPLICATIONS
Both Novatek and Orise have started mass production by shipping the LCD drivers with Full HD frame buffer and TITC image compression IP of 2 times ratio. Korean Magnachip has implemented TITC 2x/3x times IP and starts mass production in world top smart phones. The 3x/4x times IPs are integrated in most world top smart phones and will available in the market in months. TITC 6X times IP has been in most Japan and Korea TCON/TV system since 2009 which technology is modified to fit into smart phone display driver. LCD Driver chips from most world top smart phone system vendors including Samsung, LG, SONY, HTC, Huawei, Lenovoâ¦have integrated TITC compression IPs. Smart phone display resolution size ranges from WGA (800x480), Full-HD (1920x1080) to WQHD(2560x1440) and display rate ranges from 30Hz, 60Hz (default), 90Hz to 120Hz which requires transmission and receiving bandwidth ranges from 600M bps to 11G bps is quite heavy load in transmission. Higher clock and data transmission speed triggers headache of EMI issues. Taking the Full HD resolution as an example, a 60 Hz display requires a total of 3G bps (1902x1080x24x60) which requires 4 MIPI lanes with clock rate of ~1GHz and consumes ~5mW in transmission and receiving nodes. TITC proposes image compression solution to minimize the data amount to transmit and to reduce the power consumption on MIPI bus and to cut down the requirement of the transmission bandwidth hence eases the headache of EMI issues.
Some control registers are implemented within TITC lossless compression IP to select the targeted frame resolution, display/refreshing rate. Depending on the bandwidth requirement, a corresponding compression ratio will be selected and the compression engine will be enabled to compress and transmit the compressed pixels to the display panel, and the display drive will get information of the frame size and the compression ratio so that the driver can decompress it appropriately before driving it out to the display panel.
This LCD display driver with Full HD frame buffer and 2X times image compression IP runs up to 250M Hz with SRAM synchronized clock rate enters mass production in most world top smart phones since mid 2013. Depending on the bandwidth requirement, the configurable register selects one of the 4 compression ratios, say 2x/3x/4x/6x, so that TITC compression engine can reduce the image data to meet the data rate for transmission. These Display Drivers with TITC compression IP reduces the frame buffer density as well lower bandwidth requirement in transmitting image from the AP chip to the display panel driver hence eases the headache of transmission-receiving bandwidth by reducing the MIPI clock rate from 1G Hz down to 500M Hz or even 166M Hz when 6X times IP is ready late 2013.
The authors would like to express their appreciation to R&D teams of TITC, Novatek, Orise and Magnachips as well as Mr. Herve PIERROT, a design manager at ST for their excellent and hard work on the system design and FPGA porting. Dr. Fritz Lebowsky has in the past years provided lots of expertise in image quality enhancement which plays a critical role for the superior image quality of this work.
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