Bhanu Khera and Harsh Garg, Freescale Semiconductor India
embedded.com (January 26, 2014)
With shrinking technologies, rapid multiplication of clock frequencies, and increasing emphasis on power reduction, low-power design is taking on a vital role. Design teams can no longer afford to worry only about isolation on big power domains. With most SoCs containing multiple sequential circuits, every little bit counts, thus making it all the more important to design efficient low power designs. These sequential circuits are predominantly used to design finite state machines (FSMs), clock dividers, and counters in modern day designs.
This article describes an efficient way to design low power sequential circuits with effective clock gating with the help of a multi-stage programmable Johnson counter that can be extended to support a wide range of dividing factors, while consuming lower dynamic power compared to conventional circuits.
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