Arjun Pal Chowdhury, Neha Agarwal, and Ankush Sethi, Freescale India
embedded.com (August 13, 2014)
In a sequential system on chip designs, if the reset of source register is different from the reset of destination register, even though the data path is in same clock domain, this can cause an asynchronous crossing path to occur which can cause metastability at destination register .
This paper proposes a verification tool flow which can be used with any SoC structural verification tool to detect such reset domain crossing (RDC) problems. It also describes some techniques to make the SoC design tools you use intelligent enough to weed out false violations.
Click here to read more ...