Efficient Buffer design for Hold fixing

Shekhar Arya, Sriram Gupta, Gaurav Goyal; Freescale Semiconductor India Pvt. Ltd.

In a current trend of SoC Design, IC’s are becoming more and more complex so the challenges of meeting all the design requirements have become increasingly difficult. Noise becomes prominent in lower technology nodes. Expectations from current SoC’s are high noise immunity, low power design and reduced die size. Though, it is impossible to meet all of these but what designers can ensure is that try to meet all of them to the extent such that there is no loss in other specifications.

In shrinking technologies, all SoC’s have to work in multi modes and multi corners. So there is a tough challenge to meet setup and hold in all corners. Hold violation closure for a design involves Non-Si Hold closure (due to clock - skew) & Si Hold closure (due to clock and data noise). Non-Si Hold fixing is done by downsizing the existing logic or by putting more hold buffers in the path (primarily of Low drive buffers) while the Si-Hold fixing can be done by adding more buffers.

Since delay is reversely proportion to drive strength, low drive strength cell is chosen for hold fixing. These buffers are normal buffer cell with very less drive strength capability. These buffers have their own limitation. They are more noise prone cells. If there is huge timing violations, a chain of buffers are used and so local density becomes high. Below is comparison between Non-Si & Si Hold profiles in any typical design in the Table 1.

Non-Si and Si Hold comparison Table on a typical design:

	WNS	TNS	No. of Paths
Non-Si Hold	-0.65 ns	-41.02 ns	340
Si Hold	-1.016 ns	-340.228 ns	1294

Table1. Comparsion between Si & Non-Si hold fixing in any design

Contribution of noise from various elements in noise:

20-25% is from clock noise
50-55% logic data path elements
15-20% is from hold buffers added in the design

Below is the Fig. 1 which depicts a conventional Buffer design which has been used for the hold fixing.

Fig. 1 Conventional Buffer Cell Design

The conventional buffer design is not able to provide the desired delay needed for hold fixing & if a more low strength buffer needs to be used for more delay then that buffer suffers from noise. So, all these shortcomings led us to think of a new architecture of buffer which is capable for meeting hold timing without any impact in area, having a high delay with same noise immunity. i.e. a cell with more delay & with the same drive strength so that it’s noise immunity also remains same.

For the new proposed buffer cell design , transistors Ma & Mb have been added which are ALWAYS ON to provide the necessary required delay without affecting the input capacitance of the cell as can be seen from the below Fig. 2. Since, our aim was to fix hold violation. By this way we have increased the cell delay and also kept the same noise immunity.

Fig. 2 Proposed Buffer Cell Design.

During designing of this cell we ensured there is no impact on area and power. Since the proposed cell has higher delay without any impact in area, local congestion issue can also be solved. The new architecture cell is designed such that it takes same area as the conventional cell but provides more delay. So, while talking about the whole design which is hold critical, same timing requirement is achieved by using less number of new architecture buffers. So in that way less congestion as compared to the same design with conventional buffer used. Below are spice simulation results for the comparison between the conventional design v/s proposed design at a cell level:

Table2. Spice results between conventional & proposed hold buffer

Design Results: We picked a design and did Noise hold fixing with:

Run1: Conventional buffer only.
Run2: Using proposed buffer only.

& below are the results:

Table3. Comparison between conventional & proposed hold buffer usage in a design

Due to the 20-25% saving in the number of hold buffers used, there is overall decrease in the leakage and dynamic power of the design i.e. by ~2.75 % while it is more for the individual cell comparison between conventional v/s proposed circuit as can be seen from the Table 2. Routing overhead is also less for hold fixing, less problem of local congestion. Area is also saved due to less number of buffers used.

Conclusion:

As per the above analysis, the proposed buffer cell is capable to fix the HOLD violations more efficiently as compared to the existing buffer cells & saves area, power & routing effort. Generally designers are chasing the high performance targets. All designs can use the proposed design architecture. Hold critical designs or congested design would be more beneficial from this circuit and also cycle time of any SoC can be reduced.