English
FPGA constraints for the modern world: Product how-to
Joe Mallett, Synopsys
EDN (July 04, 2016)
Today’s FPGAs are larger and more complex than ever, and defining and applying correct design constraints is one of the biggest challenges. When the design fails to meet the timing performance requirements it can be very time consuming to find the issues, but the process is made easier with well-defined constraints.
Constraint setup can be a daunting task, and synthesis tools such as Synopsys’ Synplify Pro and Premier can help with automatic template creation, “autoconstraining” of new designs, setup and import of IP-specific constraints, and forward annotation to place and route software.
This articles details how Synplify, a timing-driven synthesis tool, enables designers to develop and apply correct timing constraints to achieve good quality of results (QoR). The following are the design elements that FPGA designers should consider when developing constraints:
- Identify clocks
- Identify and creating clock groupings and clock relationships
- Constrain clocks
- Constrain inputs and outputs
- Define multi-cycle paths and false-paths
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
New Articles
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Synthesis Methodology & Netlist Qualification
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- UVM RAL Model: Usage and Application