Next-gen DSL: SoC doubles the data rates

By far the most popular form of consumer DSL is asymmetric digital subscriber line. In its current form, ADSL supports maximum downstream (from telephone central office to the home) data rates of 8 to 10 Mbits/second over relatively short loop lengths. ADSL can reach up to 18,000 feet with meaningful downstream data rates. Additionally, the emerging ITU ADSL G.dmt.bis (ADSL2) standard will increase the maximum downstream data rate to approximately 12 Mbits/s in its basic form by making the S = 1/2 coding option mandatory, which is an optional feature in the current ITU G.992.1 (G.dmt) standard. With minor enhancements in transmission technology, G.dmt.bis will also extend ADSL's meaningful reach by 5 to 10 percent.

We propose two powerful techniques for implementation with ADSL2: ADSL2+ and reach-extended ADSL (READSL). These techniques will dramatically improve both data rates (up to 20 Mbits/s in the downstream direction with ADSL2+) and reach (up to 35 percent longer with READSL) over standard ADSL today.

In many ways, ADSL2+ is a natural extension of the current standard ADSL, utilizing discrete multitone (DMT) modulation with twice the transmission bandwidth, from roughly 1.1 MHz to 2.2 MHz. To achieve that, the number of downstream subchannels is doubled from 256 to 512, all the while maintaining the same subchannel bandwidth or tone spacing of 4 kHz. Over short to midrange loops, the additional downstream transmission bandwidth allows higher data rate transfer. In fact, in a wide variety of transmission environments, the achievable downstream data rate of an ADSL2+ connection will double that of an ADSL connection; for example, when the loop is less than about 6 kilofeet in length. There is still significantly higher achievable data rate all the way up to 9,000 feet when comparing ADSL2+ connections with corresponding ADSL connections. By contrast, over very long loops, the additional downstream transmission bandwidth is no longer useful because the extra subchannels in the higher frequency region are too severely attenuated to support reliable data transmission; thus they revert back to the standard ADSL.

READSL technology complements ADSL2+ because it improves the reach of ADSL over very long twisted pairs (up to 22 kfeet). This is accomplished by taking advantage of DMT modulation and varying the partitioning of the upstream and downstream transmission bands to optimize for reach. In particular, for longer loops, the downstream transmission capacity will typically limit the reach because channel attenuation is greater at high frequencies and where downstream data is transmitted as specified by the ITU ADSL standards. By varying the frequency bands used for downstream and upstream transmissions, we can improve the overall throughput rate of the READSL system over very long loops. For example, the achievable reach of a DSL connection at a downstream data rate of 192 kbits/s can be extended from approximately 18.5 kfeet to 22.5 kfeet with READSL-enabled modems.

Packing it in

Both ADSL2+ and READSL can be realized with highly integrated silicon implementation. In particular, it is highly cost-effective to have a single-chip, system-on-chip (SoC) implementation of a next-generation ADSL customer-premises modem that is capable of ADSL2+ data rates and READSL loop reach. This system-on-chip ADSL customer-premises equipment (CPE) will include a line driver capable of ADSL2+ and codec block, a digital signal-processing engine block and a network processor block, all on one monolithic die. It also should have a number of interfaces to various types of home-networking devices, such as an 802.11 wireless LAN, an Ethernet router or a PC via a USB interface.

Integration of a line driver capable of ADSL2+ with the digital sections presents a significant design challenge due to the high voltages being introduced into a CMOS process. It provides significant benefits, however, from cost savings, tighter integration of filters and overall reduction in board layout complexities. The integrated codec block requires programmable filters that allow for a complete selection among the various flavors of ADSL, including Annex A, Annex B, Annex C, ADSL2+, ADL (all-digital loop) and READSL. These programmable filters are a key requirement to properly support ADSL2+ and READSL within the same chip. The programmable nature of the filters also benefits interoperability, as every digital subscriber line access module requires slightly different filter settings to maximize performance.

Because ADSL2+ doubles the number of downstream tones to achieve the higher data rates, a highly flexible a rchitecture, including a programmable digital signal processing (DSP) core, is ideal. This architecture allows the size of the fast Fourier transform function to be doubled while in ADSL2+ mode, but it also allows for performance enhancements in the normal ADSL mode with the extra Mips and memory.

Particular design attention needs to be paid to various areas of the DSL physical-layer (PHY) subsystem to support the higher downstream data rates of ADSL2+. Some of these areas include the DSP core speed, memory size, internal data buses and direct-memory-access operation. Functions such as the asynchronous transfer mode (ATM) transmission convergence (TC) layer can either be done in software or in hardwired gates, depending on the system trade-offs. For example, the ATM TC layer can be implemented as a hardware block connected to the DSP core on a high-speed bus.

The networking subsystem should be designed to sup port not only the higher data rates but also various new applications that ADSL2 and ADSL2+ enable.

For example, the number of VPI/VCI combinations that the asynchronous- transfer-mode segmentation-and-reassembly chip could handle should be at least 16 to 32, and additional ATM quality-of-service features should be readily implemented on the programmable RISC core.

Finally, numerous interface blocks need to be designed to support the higher data rates and applications that ADSL2, READSL and ADSL2+ enable. The SDRAM interface and memory controller should be designed so that multiple paged memories can be kept open simultaneously.

Wait states slashed

Such an arrangement greatly reduces the number of wait states that are required to access SDRAM. An internal 10/100-Mbit/s Ethernet PHY should be present, and that implementation can be complemented by an additional 10/100 Ethernet media-access controller that can be used for multiport Ethernet applications.

The devic e should also have a high-speed interface that connects directly to various flavors of 802.11a/b/g wireless-LAN devices that can support 50-Mbit/s or faster operation.

The advent of new technologies and standards in DSL will enable many new consumer applications and stimulate rapid growth of broadband access to the home. ADSL2+ will effectively double the achievable data rate of ADSL and deliver a host of video-based services to the consumer. READSL, meanwhile, will extend the meaningful reach of ADSL to achieve nearly ubiquitous coverage.

Employing the latest silicon process with a flexible systems architecture, a single-chip SoC implementation of an ADSL-2+/READSL-ready CPE modem can be expected to change the landscape of digital subscriber line deployment. Such an approach will offer a highly cost-effective and future-proof solution that will readily enable a broadband, connected home when combined with a networking device such as an 802.11x wireless local-area network.

Peter S. Chow is CTO and William A. Santini is engineering manager at the DSL Technology Center of Texas Instruments Inc. (San Jose, Calif.). Chow can be reached at pete@ti.com.

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