ASIC technology is morphing as demand for custom chips remains solid despite rising mask costs and slow growth in many end markets.
By Corinne S. Bernstein
08/04/2003 12:00 PM EST
The ASICs business is a study in market dynamics and supplier adaptation. Although industry watchers expect the sector to grow the next few years, declining ASIC design starts will conspire to offset rising revenue and an increase in unit volume per design.
Of course, ASICs have survived years of technological and business challenges, and the advent of competing "ASIC lite" designs is not seen as signaling the market's demise.
"Talk of the death of the ASIC market resurfaces every few years because of the rising costs and complexity of the devices and the growth of alternatives," said Bryan Lewis, an analyst at Gartner Dataquest, San Jose. "But ASICs continue to evolve and adjust to market conditions."
Most ASIC suppliers are looking at options aimed at broadening their appeal. One option earning industry attention is the platform ASIC, which combines preconfigured and custom features. Despite its potential, however, it is too early to judge how platform ASICs will affect the market's long-term outlook, according to Lewis.
Dataquest estimates that worldwide ASIC revenue this year will reach $16.9 billion, up 6% from $15.9 billion in 2002. The research firm projects a compound annual growth rate of 8.4% from 2002 to 2007, when the ASIC market will achieve $23.9 billion.
The decline in new designs will continue but at a more moderate rate, according to Lewis, who estimates that ASIC design starts numbered 3,500 to 4,000 last year, down from about 11,000 five years ago.
Analysts at iSuppli Corp., El Segundo, Calif., also anticipate a more modest decline in design starts the next few years, but are less optimistic than Dataquest about the market's revenue prospects. According to iSuppli, the number of revenue-capable ASIC designs started in 2002 dropped 28%, to 1,450 from about 2,000 in 2001.
"While the average revenue associated with each design is increasing, this is not enough to offset the reduced number of designs and, as such, this trend will depress the ASIC market in the 2005 time horizon and beyond," iSuppli said in a report.
Although analysts' estimates for revenue and design starts differ, they agree on the underlying market dynamics. As a result of the three-year industry slump, there have been far fewer slots to fill in the key industry sectors that consume ASICs.
Consumer, data processing, and storage applications historically have accounted for a large share of the ASIC market--nearly two-thirds of designs and three-fourths of revenue, according to iSuppli. The wired and wireless communications segment, which led to stellar ASIC growth in the late 1990s, accounted for only 14% of designs and revenue last year.
Advances in technology are also to blame for declining design starts. Integration has reduced the number of chips in each system but increased the value of each device. "What once required four chips now uses one or two," Dataquest's Lewis said. "The functionality hasn't gone away; it has been combined into one higher-value chip."
Contributing substantially to the erosion in design starts is the transition to smaller line geometries, which has increased design complexity, development time, and cost. While some ASIC vendors are completing the shift to 0.13-micron processes, others are honing their 90nm technology, which they expect to take off next year.
Mask and wafer costs are estimated at $1.3 million for 90nm technology, compared with $900,000 for 0.13 micron and $400,000 for 0.18 micron, according to data from Cary Snyder, an independent semiconductor industry analyst based in San Jose. Tack on another $5 million to $10 million for other costs, including engineering and design tools, he said.
Whenever the industry transitions to a new geometry, a new set of challenges crops up, said Rich Wawrzyniak, an analyst at Semico Research Corp. in Marrietta, Calif. "There are more features on a die, more people involved, and it takes longer. There's also a temptation to add more stuff when you go to smaller design rules."
Systems makers face a classic Catch-22. Using an ASIC can be expensive, but choosing another option also can be costly.
"The ASIC is still the absolute lowest-cost solution because it is tailor-made for the application," Wawrzyniak said. "General-purpose devices could cost more in the long run."
Choosing an ASIC vs. an ASSP, FPGA, or other technology creates cost/performance issues that affect time-to-market, life span, and overall system maintenance, according to Mobashar Yazdani, ASIC program manager in the Electronic Systems Technology Group at Hewlett-Packard Co., Palo Alto, Calif. There's a lot of pressure to go to ASSPs, but in some cases ASICs are the best alternative because they enable product differentiation, Yazdani said.
"ASICs are the product's personality, but it depends on the application. The ASIC's benefits outweigh its costs in high-volume products like printers."
ASICs offer the lowest unit price, highest performance, and most flexibility, said Necip Sayiner, vice president of the networking ASIC business at Agere Systems Inc., Allentown, Pa.
Cell-based designs carry high nonrecurring engineering (NRE) charges but significantly lower unit costs than ASSPs and FPGAs. As development costs climb, however, a larger revenue stream and higher unit volumes are required for an ASIC to be an economically viable choice for the customer, said Stephen Sutton, vice president of Texas Instruments Inc.'s ASIC business in Dallas. As demand has weakened in optical networking, for example, it has become more difficult to justify using an ASIC, and design starts in that sector have dropped, he said.
"Customers using ASICs are taking a bet they can pay back development costs," Sutton said.
The "NRE break-even point" used to be 1,000 units; today, it's 2,000, said Tom Reeves, vice president of IBM Microelectronics and general manager of the company's ASIC business in Burlington, Vt. "Our average piece of business is 50% larger in 2003 than projects started a year ago," he said.
This actually creates some significant benefits. Running fewer part numbers in higher volumes means more efficient manufacturing and lower costs to buyer and seller. And, because the stakes are higher, customers must be more choosy, which helps boost the life expectancy of each ASIC and its revenue potential, said Benson Cheung, director of business development at the System LSI Division of Samsung Semiconductor Inc., San Jose.
"Customers are doing better due diligence before committing resources to make sure that products have the potential for high volume," Cheung said. "Once we engage in design with customers, there's a better chance of the design going into high-volume production."
Platform ASICs have been gathering steam in the last few quarters because of their potential to reduce NRE costs as well as design complexity and speed development. Although platform ASICs have significantly higher unit costs than standard cells, the devices don't require the high unit volumes and revenue stream needed for full-custom chips.
"While the standard cell will drive toward ultrahigh performance, where cost is not an issue, or the consumer market, where there is ultrahigh volume and an increasing appetite for performance, platform ASICs are becoming essential as design centers move to 0.13 micron," said Dave Holt, president and chief executive of Lightspeed, Sunnyvale, Calif.
One type of platform ASIC is the structured ASIC in which diffusion layers and polylayers form an established structure of logic cells, tied together with a few additional layers of metalization that can be customized later.
Chip Express, Fujitsu, Lightspeed, LSI Logic, and NEC are taking an embedded gate-array approach. In this type of structured ASIC, the fixed IP includes the DRAM controller, memory, PCI, and processor core, while the vertical-market IP and metal programmable gates constitute the customizable portion of the devices.
The structured ASIC's complexity is hidden from the customer, who still determines the final device configuration and is responsible for system-level verification, according to Keith Horn, vice president of marketing at Fujitsu Microelectronics Inc., Sunnyvale.
Structured ASIC tools can be written faster, design and manufacturing are quicker, and there are fewer mask steps. The technology can be used for proof of concept or for the life of a system, Horn said.
AMI Semiconductor's hybrid gate array, built on an 0.18-micron process, is aimed at medium-density, low-power ASIC applications and FPGA-to-ASIC conversions. The first few layers are put on during the front-end fabrication at Taiwan Semiconductor Manufacturing Co. Ltd., and three to five layers are added at AMI's fab.
The result is lower tooling costs and NREs, and about a 10-day lead time for prototyping, compared with 20 to 25 weeks for cell-based technology, according to Vince Hopkin, vice president of digital ASICs at AMI, Pocatello, Idaho.
Chip Express, which announced its late-stage programmable Advanced Gate Array ASICs earlier this year, is working on an 0.13-micron version of the structured array, said Doug Bailey, vice president of marketing in Santa Clara, Calif.
Others are taking the 90nm plunge.
NEC Corp. expects to be in production in mid-2004 with the latest version of its platform ASIC, made on a 90nm process. The offering, which will provide up to 4 million usable gates, 10Mbits of embedded configurable memory, and performance up to 500MHz, has a design of five to seven metal layers with two customizable layers.
Another take on the structured ASIC, Altera Corp.'s HardCopy, shares the same basic process technology and I/O structure as an FPGA. The device uses Altera's Stratix FPGA technology, but the programmable elements are removed and replaced with the customer's programming files, said vice president of product planning Robert Blake, San Jose.
"Stratix is an FPGA, but when it is converted into HardCopy it looks like a structured ASIC but could also be used as an ASSP."
Some platform ASICs don't take a structured approach.
Toshiba's SOC MOSAIC incorporates commodity IP blocks, standardized bus interfaces, and a scalable bus system--a configuration that helps reduce time-to-market to as little as six months, according to Richard Tobias, vice president of ASIC and foundry business units at Toshiba America Electronics Corp. in San Jose. Each chip is laid out from scratch rather than using fixed pieces of silicon, which can create frequency and timing problems, he said.
"You can still tailor the chip to the application, but the ability to get time to market is fast," Tobias said. "If you waste time, you can spend mask costs. Because of cost savings, you can sell to low- or high-volume customers."
Hybrid solutions like platform ASICs pose definition issues, iSuppli's Selburn said. "The question is whether that is an ASIC or an ASSP. And it remains to be seen how they will compete with standard cells, PLDs, and standard products."
If the platform technology is categorized as an ASIC, that will help bolster ASIC design starts, according to Ronnie Vashista, vice president of technology marketing at LSI Logic Corp., Milpitas, Calif.
Prognosticators at LSI Logic estimate the platform ASIC total available market at $7.1 billion this year and $9.3 billion in 2006. These projections are predicated on the technology's potential to capture 30% of the cell-based ASIC business, 35% of high-end FPGAs, and 15% of ASSPs.
At the end of the day, however, the changing ASIC market probably won't affect overall semiconductor revenue, according to Ray Cornyn, operations manager for the 32-bit consumer business at Motorola Inc.'s Semiconductor Products Sector in Austin, Texas.
"If ASICs decline and ASSPs become more prominent, for example, we recognize that to satisfy the market, you normally have to have a range of products," Cornyn said. "In terms of the overall semiconductor market, you might see a shift in where the revenue comes from."
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