Featured Article
In this paper we will be discussing about the importance and completeness of verification planning in order to achieve the verification requirements and reuse techniques adapted during the planning phase to enhance reuse between different cores based designs.
Featured Article
When planning a complex product development project using an ASIC or SoC it is critical to analyze the various risks, project costs, resources required, and expertise required in order to allocate resources (money, equipment and people) to maximize the profit potential of the product. At MemCore we believe that many times this analysis does not include many of the key ''hidden'' costs and risks associated with the implementation of a complex memory interface solution (memory controller).
Featured Article
In this paper, we describe the methodology for designing a library which produces low power and lower leakage designs. This approach of designing standard cell library does not require any CAD tool or ASIC design flow changes, nor does it require any process changes. The topology of each standard cell and the gate length of each transistor are unchanged. The innovation relates to how cell drive strength should be determined.
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