D&R Industry Articles: SoC (System on Chip), Silicon IP, Semiconductor IP, Software IP, Verification IP, Core, Design Reuse


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Articles for the Week of Jun. 28, 2007



Featured Article Verification Planning for Core based Designs In this paper we will be discussing about the importance and completeness of verification planning in order to achieve the verification requirements and reuse techniques adapted during the planning phase to enhance reuse between different cores based designs.
Additional Articles
Data compression tutorial: Part 3
Commentary: SystemVerilog enables design with verification
Analog behavioral models reduce mixed-signal LSI verification time


Articles for the Week of Jun. 22, 2007



Featured Article The Impact of Make vs Buy Decisions for Memory Interface Solutions When planning a complex product development project using an ASIC or SoC it is critical to analyze the various risks, project costs, resources required, and expertise required in order to allocate resources (money, equipment and people) to maximize the profit potential of the product. At MemCore we believe that many times this analysis does not include many of the key ''hidden'' costs and risks associated with the implementation of a complex memory interface solution (memory controller).
Additional Articles
Software-Intensive ASICs/ASSPs Demand Integrated Prototyping Solutions
A Multi-Objective Optimization Model for Energy and Performance Aware Synthesis of NoC Architecture
How customer-specific standard products ease mobile device design
STBus complex interconnect design and verification for a HDTV SoC
Design Constraint Verification and Validation: A New Paradigm
Practical Power Network Synthesis For Power-Gating Designs


Articles for the Week of Jun. 14, 2007



Featured Article Designing Low Power Standard Cell Library With Improved Drive Granularity In this paper, we describe the methodology for designing a library which produces low power and lower leakage designs. This approach of designing standard cell library does not require any CAD tool or ASIC design flow changes, nor does it require any process changes. The topology of each standard cell and the gate length of each transistor are unchanged. The innovation relates to how cell drive strength should be determined.
Additional Articles
Verification of a single-chip Analog TV and Digital TV ASIC
Using customizable MCUs to bridge the gap between dedicated SoC ASSPs, ASICs and FPGAs: Part 1
OTP for DCP Key Storage
Tested and effective methods for speeding up DSP algorithms


Articles for the Week of Jun. 07, 2007



Featured Article FPGA Prototyping of Complex SoCs: RTL code migration and debug strategies In this paper, RTL migration and debug strategies are presented, which needs to be skillfully handled to meet the said criteria. This paper is backed up with vast FPGA prototyping experience of various SoCs with logic gate count up-to four million.
Developing a Reusable IP Platform within a System-on-Chip Design Framework targeted towards an Academic R&D Environment
Using FPGAs to interface with digital communication protocols
Floating- to fixed-point MATLAB algorithm conversion for FPGAs
Video over IP with forward error correction (FEC)