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Headline (August 2007) Sign Up for SoC News Alert  |
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| Articles for the Week of Aug. 30, 2007 | |
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Featured Article
Distributed Software Behaviour Analysis Through the MPSoC Design FlowThe complexity of developing Systems-on-Chip (Soc) is increasing continuously, but the productivity of hardware and software developers is not growing at a comparable pace. As a consequence, the conception of a new SoC can take a few years and software can’t wait its availability. |
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| Articles for the Week of Aug. 23, 2007 | |
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Featured Article
Smart InterConnects with Smart IP: Joint Enablers for Rapid MultiMedia SoC DevelopmentFor the past decade, the march of Moore’s “Law” has witnessed the phenomenal growth in System on Chip (SoC) gate counts, allowing the implementation of a confluence of sophisticated algorithms at price points feasible for consumer electronics (e.g., HDTVs, DVD recorders, multi-functional mobile phones, etc.). Unfortunately, gate counts over the past decade have grown far faster than IC designers’ productivity. With so much pressure to launch high end consumer products before prices (and margins) erode, generations change, new standard features are added, and additional competition surfaces, every aspect of the design flow requires analysis to see how, if, when, and where time-to-silicon can be shortened. |
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| Articles for the Week of Aug. 16, 2007 | |
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Featured Article
IP Core for RAID 6 Hardware AccelerationAs storage requirements and magnetic disk densities increase the need for reliable storage solutions also increase. This IP core, written in Verilog HDL, provides a small and efficient hardware accelerator for performing RAID 6 calculations to provide uninterrupted access to data during both single and double disk failures. |
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| Additional Articles | |
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| Articles for the Week of Aug. 09, 2007 | |
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Featured Article
Systel Level Design Automation of Pipelined ADCIn this paper a design automation technique for pipelined analog ¨C to ¨C digital converter (ADC) is presented, the aim is to automate the design of a switched capacitor pipelined analog ¨C to ¨C digital converters and to extract the circuit level specifications (spec¡¯s) from system level by modeling the most important circuit non-idealities effects on effective number of bits (ENOB). |
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| Additional Articles | |
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| Articles for the Week of Aug. 02, 2007 | |
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