D&R Industry Articles: SoC (System on Chip), Silicon IP, Semiconductor IP, Software IP, Verification IP, Core, Design Reuse


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Articles for the Week of Nov. 29, 2007



Featured Article Pushing the Frontier in Managing Power in Embedded ASIC or SoC Design with PCI Express This paper will discuss some techniques applicable to PCI Express such as changing device power states in coordination with operating system, managing clocks and managing device drivers. In addition, this presentation will present a trade-off analysis between latency and clock frequency with respect to power consumption.
Additional Articles
Embedded DSP Software Design Using Multicore a System-on-a-Chip (SoC) Architecture: Part 2
Viewpoint: Embrace platform-based design
Using the ARM Cortex-R4 for DSP, part 2: Software optimization


Articles for the Week of Nov. 22, 2007



Featured Article IP licensing fosters design flexibility Emerging automotive electronics design model "decouples" supplier choice from technology choice, while advancing industry standards
Additional Articles
Embedded DSP Software Design on a Multicore SoC Architecture: Part 1
Designing a CMOS synthesizer RFIC
Using the ARM Cortex-R4 for DSP, part 1: Benchmarks
OCP SoC instrumentation solutions involve more than just trace


Articles for the Week of Nov. 15, 2007



Featured Article Configuration-based Environment that Supports Scalable PHY Verification Leading-edge analog/mixed-signal design requires custom flows built with a variety of tools that use a multiplicity of design representations. When it is a centralized resource, a single verification team may be faced with overwhelming complexity when supporting multiple design teams, each with multiple tools and a variety of design representations.
Additional Articles
Generate FPGA designs from M-code
Light-weight Communication Infrastructure for IP Integration
Design with Verification: Not an Oxymoron
Insights using NAND flash in portable designs


Articles for the Week of Nov. 08, 2007



Featured Article Formal Verification IPs: the corner stone for a broader adoption of Formal Verification In this article we show how several areas of the functional verification task can benefit from automated formal verification: design coverage enhancement, protocol compliance checking and functional performance analysis. With our proposed methodology, these tasks can be achieved seamlessly by designers or verification engineers, thus bringing more automation and robustness to the verification of SoC designs.
True design-for-manufacturability critical to 65-nm design success
Using Serial RapidIO for FPGA co-processing
How designers can survive the embedded multiprocessor revolution
Tips to leveraging pre-integrated systems: How to get your application to market in 12 months