D&R Industry Articles: SoC (System on Chip), Silicon IP, Semiconductor IP, Software IP, Verification IP, Core, Design Reuse


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Articles for the Week of Sep. 29, 2008



Featured Article IP Gate Count Estimation Methodology during Micro-Architecture Phase This paper presents challenges of gate count estimation during early architecture design phase along with effective methodology. This paper is backed up with vast experience of various IP designs with logic area up-to several hundreds of kilo gates with several hundred kilo bits of memory.
Additional Articles
Measuring Quality in Semiconductor IP
Using micro-benchmarks to evaluate & compare Networks-on-chip MPSoC designs


Articles for the Week of Sep. 25, 2008



Featured Article Bridging the DFT and Product Engineering Gap to Achieve Early Silicon Validation This paper introduces a unified DFT - PE Methodology, aimed at providing a complete, methodical and fully automated path addressing gaps between DFT and PE team ensuring quick turnaround time in silicon validation.
Additional Articles
How to use FPGAs to develop an intelligent solar tracking system
Choosing the right low power processor for your embedded design
Implementing the right audio/video transcoding scheme in consumer SoC devices


Articles for the Week of Sep. 18, 2008



Featured Article Performance Verification Methods Developed for an HDTV SoC Integrating a Mixed Circuit-Switched / NoC Interconnect (STBus/VSTNoC) This paper presents the performance verification methods that were set up and used for a SoC recently developed at STM. The SoC is a one-chip satellite HDTV set-top-box decoder IC. It integrates many memory-bandwidth demanding IPs sharing one or two DDR2 memories.
Additional Articles
Using static analysis to diagnose & prevent failures in safety-critical device designs
How to defend against the cloning of your FPGA designs
Systolic FIR Filter Based FPGA
Speeding up the CORDIC algorithm with a DSP


Articles for the Week of Sep. 11, 2008



Featured Article An HDTV SoC Based on a Mixed Circuit-Switched / NoC Interconnect Architecture (STBus/VSTNoC) This paper presents the interconnect solution adopted for an HDTV SoC developed in HVD division of STM. The SoC is a one-chip satellite HDTV set-top box IC developed in 65nm technology. The interconnect of this HDTV SoC is the first in STM implementing a mixed architecture based on the circuit-switched interconnect named STBus and the new NoC interconnect named VSTNoC.
Additional Articles
A FPGA-Based Solution for Enforcing Dependability and Timeliness in CAN
Dynamic reconfiguration is transforming the embedded world
Building a configurable embedded processor - From Impulse C to FPGA
Reducing Power Consumption in a Fiber Channel Switch
Reinventing JTAG for SoC debugging


Articles for the Week of Sep. 04, 2008



Featured Article LDPC (Low Density Parity Check) - A Better Coding Scheme for Wireless PHY Layers 802.16e standard known as the Mobile Wimax standard integrates various coding schemes in the Physical layer specification including the most efficient ones, the LDPC. In this article we will present the physical layer baselines, we will then focus on the error correcting codes to finally detail our implementation.
Architecture-oriented C optimization, part 2: Memory and more
Architecture-oriented C optimization, part 1: DSP features
Bridging options enable FPGA-based configurable computing
Extreme Design: Ultra-compact embedded computer overcomes multiple design challenges
Multi-channel surveillance DVR design