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Headline (February 2009) Sign Up for SoC News Alert  |
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| Articles for the Week of Feb. 27, 2009 | |
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Featured Article
How High-Level Synthesis Can Raise the Efficiency of Design ReuseIn this paper we present a design methodology based on high-level synthesis that allows retargeting functional IPs in the form of C++ programs to technology optimized RTL implementations. We will expose results that show that this approach can eliminate the usual compromise of design quality versus design time imposed by design reuse strategies, yielding optimal implementations in very short time. |
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| Articles for the Week of Feb. 19, 2009 | |
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Featured Article
Refactoring to Prepare RTL for ReusePreparing a design for reuse, especially one not originally written with reuse in mind, often requires changing the RTL. Ideally, these changes should be made as quickly as possible and without introducing bugs. In this paper we introduce RTL refactoring as an efficient and safe mechanism for making such required RTL changes. Finally, we present a case study of applying several RTL refactors to Intel production-level SystemVerilog RTL so that it can be reused by another team. |
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| Articles for the Week of Feb. 13, 2009 | |
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Featured Article
Migrating from SPI 4.2 to SPI 5 IP Core - Architectural Changes and Re-usabilityThis article discusses the architectural changes and IP re-usability scope for modifying an existing SPI 4.2 Transmitter and Receiver IP Core. SPI 4.2 and SPI 5 have a great deal of functional similarity which makes this IP migration smoother. The paper considers an existing SPI 4.2 IP core and examines the architectural changes and re-usability of the sub-modules. The addition of a few modules, which are a part of SPI 5 protocol, is also highlighted. |
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| Articles for the Week of Feb. 05, 2009 | |
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Featured Article
A Platform for Performance Validation of Memory ControllersWith growing gap between processor and memory speeds, the memory bandwidth has become performance bottleneck for media applications. The memory controller designs are getting optimized to reduce the latencies added by them. It is necessary to prove the performance of memory controller on prototypes. It has been observed that the performance calculated in simulations is very difficult to achieve on prototype board. This is mainly because of subsystem limitations. |
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