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Cisco’s Visual Networking Index forecasts that the Internet growth will quadruple by 2013. Projected Internet traffic will approach 1 Zettabyte (1 trillion Gigabytes) per year. To support this amazing trend, the next generations of networking equipment must offer new levels of packet forwarding rates and bandwidth density. This in turn will necessitate new generations of packet processors and the memory subsystems to support these increased demands. MoSys is stepping up to this challenge by introducing a new class of device to accelerate access to packet forwarding information, statistics calculations and packet storage.
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This paper elaborates on the advantages of continuous integration for FPGA SoC projects, reports on real-world usage of CI for the design of a scalable video decoder and provides some guidelines for setting up a new continuous integration system.
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The increasing structural complexity and the decreasing size of integrated circuits, associated with the reduction on design time, demands that the hardware designer uses a very well planned design flow to obtain high quality IP-cores. With increasing demand on more complex IP-cores, mechanisms for guaranteeing the design quality are being standardized and must be included in the design flow. The DO-254 standard is an example of such standardization for airborne systems.
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