Design Reuse
Search EETimes
Silicon IP Verification IP Software IP Wanted IP !!! Free Download IP Analytics (Restricted Access) FPGA Board / Kit Design Services Foundries Main IP/SoC Products Embedded Systems Design Platform / Structured ASIC Foundries FPGA / CPLD Fabless / IDM Deals Legal Business Financial Results People ESL Design Commentary / Analysis Main Silicon IP / SoC Verification IP FPGA / CPLD Embedded Systems Design Platform / Structured ASIC ESL Design ESL Design Standards & Best Practice Structured ASIC Verification IP Main On Cores Embedded Systems EDA Tools IP Cores Tool Demos D&R Partners Research / Market Reports Events Calendar Webcasts / Podcasts Online Bookstore



The challenges of next-gen multicore networks-on-chip systems: Part 2


Related Articles

Latest Articles

Most Popular (Updated Daily)

By Luca Benini and Giovanni De Micheli, Embedded.com
Feb 12 2007 (0:30 AM) -- Embedded.com

There are several hardware types of SoC designs that can be defined according to the required functionality and market. In general, SoCs can be classified in terms of their versatility (i.e., support for programming) and application domains. A simple taxonomy is described next:

General-purpose on-chip multiprocessors are high-performance chips that benefit from spatial locality to achieve high performance. They are designed to support various applications, and thus the processor core usage and traffic patterns may vary widely. They are the evolution of on-board multiprocessors, and they are typified by having a homogeneous set of processing and storage arrays.

For these reasons, on-chip network design can benefit from the experience on many architectures and techniques developed for on-board multiprocessors, with the appropriate adjustments to operate on a silicon substrate.

Click here to read more ...





   

Add your Opinion

   

 

E-mail This Article Printer-Friendly Page