Blue Catalyst
Blue Revolution in VLSI ad System Design
By Swapnil S.,



Tuesday Feb. 15, 2000

Verifying Hardware and Software Border Line

i have been ardent fan of Toyota manufacturing.Toyota was the first company who streamlined the processes and quality matrix in the factory units , established a flow and performance management in for the workers and implemented a methodology to track the production.This was indeed very different from the Ford(American) and other European companies who till then have been very much stressing on the luxury ,customization etc etc..

Toyota swept the market from its big competitors due to its new process implementation techniques which was later got fame with "TOYOTA WAY" tag..

Recently Toyota is in news again because of some bugs that have been found in its parts due to which it had to recall a few thousands of units.Experts and technologists say it was a software bug that has caused the problem.

Being a hardware engineer and that too into VLSI Chip verification,i am not much exposed to Software Test Cycles.But considering that SW has SEI and CMMi etc etc standards - i presume that Test flow must be as robust as it is in Hardware verification.Software validation has been formalized many times, by SEI thru CMMI, and in many other ways. It should have been a much more mature practice than ASIC validation.But still i doubt that ASIC functional verification has many features generally lacking in SW verification. I'm not aware that executable metric-driven verification plans, functional coverage, and constrained-random test generation are typically used in the SW world. However, that many problems occur when hardware meets software. This is where advanced functional verification methodologies from the HW world can be very useful.

What i think the problem is bound to occur in most of the occasions when there is an integration of Software and Hardware :
ASIC designers don't have the rigor or methods for software validation to apply to the drivers and such that they are validating. And software engineers don't understand everything about the hardware. Combine that with the task of integrating legacy control systems and my god its difficult integrating.

i have read a http://www.truststc.org/scada/presentations/III_2_Yazarel.pdf presentation that talks about power train control bug and the verification problems behind it which was there in the 2000 Toyota motors.The presentation was given at a 2006 SCADA (Supervisory Control and Data Acquisition) conference.It infact was written by 3 Toyota Authors and is quite interesting.The main issues that the paper has tried to address are that-there are very much legacy and gradually incremental complex control systems and multiple modules in the system that are talking and communicating to each other.

And it proposes that one need to have all this matrix in order to verify the system(HW SW border line)--
• Formal definition of multiple layers of abstraction for control system software that captures component interactions, data-access rules, and explicit/implicit dependency structures
• Formal specification of control system properties to assist validation and verification
• Hierarchical verification at the module, feature, and system levels
• Test generation for closed-loop feedback control system
• Assertion-based verification
The central problem is that software verification has no formalized methodology. Engineers basically run ad-hoc, directed tests until the clock runs out. On the hardware side we have metric-driven verification, executable verification plans, and coverage. Need for some methodology that merges or implements HW Verification concepts into Software verification and replaces ad-hoc testing of software.







Posted by Swapnil S. on Tuesday Feb. 15, 2000 | Add a Comment




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About the Author

About me: Swapnil has almost 11+ years of verification experience for System Design, ASIC/SOC and IPs. He has been exposed to various verification and Validation techniques and methodologies like Formal Verification, Assertion Based Verification, Constraint Driven Random based and Coverage Driven Verification, VMM,URM,AVM and now OVM i.e. Open Verification Methodology. Swapnil has been providing consultation to various organizations through his expertise in - System Verilog, Verilog, and VHDL ,ASIC-SOC-FPGA,Memory,Peripheral verification/ and System Validation.Swapnil has worked on the domains like Serial Interface, Wireless, SoC, Avionics and- Processor.Apart from Chip design aspect -Swapnil also work and consults on System Design -Integration, Debuggers, Tools, Scripts, Oscilloscopes, Software Drivers, Linux, DLLs , Applications and Firmware and ROM development.Other than the above mentioned subjects Swapnil writes and thinks about psychology in performance management, astrophysics, metaphysics, string theory, underpinnings of belief systems, mythology, religion, medicines, fashion, oriental sciences and arts ,food recipes, media, advertising, direct marketing, exorcism, politics, society, environment, economy and travel-travel and lots of travel.