Chronicle Technology provides on chip and ASIC ESD systems and structures to clients desiring greater IC ESD protection and immunity. Chronicle ESD specialists are known industry-wide through participation in ESDA’s Transient Latch-Up Device Testing Working Group and the Human Body Model Device Testing Working Group. Active participation in this and other symposia and related Technical Program Committees provides for our incorporating state of the art solutions into our client’s ASIC designs and when performing testing and characterization of clients’ ASICs.
Chronicle technologists have contributed to enhanced ESD IO design at Rockwell, ESS, Skyworks, Sarnoff, Conexant, Creative Labs, Leapfrog, Pictos and have consulted on IC ESD issues at scores of other semiconductor manufacturers and OEMs. Our specialists have contributed to projects defining ESD test chips down to 0.09µm, characterizing ESD test structures for multiple semiconductor processes, designing ESD networks, supervising Failure Analysis of devices suspected of an ESD or latch-up failure, defining manufacturing and or design solutions for parts that fail ESD, and working with IC and process design engineers to pre-empt ESD problems.
Patents granted to Chronicle team members include: new ballasting methods for MOSFETs, a method of sharing power bus clamps among many isolated power domains; diode optimization for RF and high speed circuits; cross power domain architectures; and bipolar transient bus clamps. Chronicle Technology of Irvine, CA develops ESD enhanced IO structures, chip-scale ESD systems, ESD test chips and performs test chip evaluation for the IC industry.
Chronicle Technology features services in the following categories:
3500 Barranca Parkway, #160
Irvine, CA 92606-8226
Phone: (949) 654-8160
Fax: (949) 654-4376