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Free Protected IP Models
These models are protected models which can be run on simulation tools and platforms. It should allow you to get interest in these IPs and to explore if they fit in your design.
| Core Name | Core Description |
| R8051XC2 | The fastest 8051 IP core from Evatronix. The R8051XC2 is over 12 times faster than the original Intel 80C51 when operating at the same frequency. |
| DP8051 | 8-bit Pipelined RISC Microcontroller (speed optimized) from Digital Core Design |
| PLLXpert Online | PLLXpert Online from ParthusCeva enables a designer to either create a custom PLL or alternatively download an existing PLL reference design that can be fine-tuned by the designer for a specific application. |
| SpRAM-BCD HAUMEA 65nm |
Front-End view generation for On-line Evaluation of sRAM generator, yielding the best in Low power and Density.
Dolphin Integration – availability: TSMC 65 nm
Dolphin Integration |
| LA16 | LA16 - Synthesizable HDL from Evatronix has 16 input channels, one clock input driving the count-and-capture action, synchronous/asynchronous RAM interface for vector storage and a serial interface compliant to IEEE 1149.1 |
Open source, Free IP Cores Projects
- OpenSPARC T1
- LEON3 Processor - synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture
- GRLIB IP-Library - Configurable AMBA bus SoC platform
- PXL-H264-ID31 - H.264 Inverse Integer Transform
- Opencores.org
- OpenSPARC T1 is the open source version of the UltraSPARC T1 processor. The UltraSPARC T1 processor with CoolThreads technology is the highest-throughput and most eco-responsible processor ever created. It's a breakthrough discovery for reducing data center energy consumption, while dramatically increasing throughput. Its 32 simultaneous processing threads, drawing about as much power as a light bulb, give you the best performance per watt of any processor available.
- The LEON3 processor is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 acrhitecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the GNU GPL license, allowing free evaluation.
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The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources. The full source code is available under the GNU GPL license, allowing free evaluation.
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The 2-D IIT core implements the algorithm by employing row-column decomposition of the data and applying a 1-D transform on the data row-wise, and then on the row results, column-wise.
- OPENCORES.ORG is a repository of open source, free IP synthesizable
blocks and supplemental prototype boards. Most of our cores are currently
under development but some are already available.
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