True DSP Synthesis for Fast, Efficient, High-Performance FPGA Implementations

Introduction: A Wall of Abstraction

Electronic products are currently seeing a phenomenal increase in the amount of digital signal processing (DSP) tasks being performed. Many of these products are now being implemented in field-programmable gate arrays (FPGAs), which can offer an order of magnitude performance increase over standard DSP chips. Today’s FPGAs offer multi-million equivalent gate counts and DSP-centric hard macros. Their new DSP-oriented FPGA architectures, combined with low development costs and timelines, make programmable logic a natural choice for high-performance DSP electronics.

There are typically two groups involved in the design and realization of DSP algorithms in hardware such as an FPGA DSP architects and hardware design engineers but there is a wall of abstraction between the architects who formulate the algorithms and the design engineers who are charged with their physical implementation (Figure 1).

With regard to the hardware design engineers, the way in which they typically visualize their world is as a collection of blocks described in a hardware description language (HDL) such as Verilog and/or VHDL captured at a level of abstraction referred to as register transfer level (RTL). The DSP functions will typically form only a portion of a larger design, and the RTL level of abstraction offers a natural staging point for integrating design blocks originating from multiple sources, including third-party intellectual property (IP). Furthermore, RTL synthesis technology is extremely mature and powerful.

This paper first considers the various techniques that have attempted to build a bridge between the DSP design and verification domain and the hardware design environment. Also discussed are the ways in which each of these conventional approaches has failed to satisfy the requirements of a modern design flow. Next, we introduce a completely new branch in DSP design methodology — true DSP synthesis — which integrates into existing design flows without any disruption. This new solution successfully bridges the gap between the algorithmic and implementation domains by automating the processes of system-level optimization and implementation-level mapping.

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