Fast Timing Closure on FPGA Design Using Graph-Based Physical Synthesis

Introduction

Technological advances in FPGA devices have created both application opportunities and, at the same time, tough design challenges for developers. In new devices, for example, logic routing rather than propagation delays dominate timing paths. Placement of logic and selecting routing to minimize delays complicates timing closure. Designers need tools that understand how to exploit the capabilities of new devices and realize their performance in applications.

Achieving FPGA performance requirements using conventional tools has traditionally involved multiple iterations through synthesis and Place & Route (P&R) to minimize routing delays. After each pass, delay information from the previous is back-annotated into the design database and used to adjust placement and routing to improve timing. The process is inefficient and the outcome uncertain because the approach implements designs in a series of disconnected steps where synthesis and optimization are separated from placement and routing which are performed only after synthesis has completed. By that time these tools may face an impossible task in achieving timing. Conventional logic synthesis fails to adequately account for routing delays and other device characteristics at the outset of the process.

What is needed is a synthesis algorithm that includes placing the design while considering routing resources and their delays as part of optimization so that the routing that follows is a straightforward task. Such an optimization process would yield predictable results with the best possible timing performance. Physical synthesis answers the requirements of FPGA designs by using accurate timing estimations of available logic and routing resources for physical optimization during synthesis. Physical synthesis is an essential enabling process in achieving highly optimized and predictable results for FPGA designs. Automated physical synthesis yields superior design performance for the majority of designs.

Expert designers can add their expertise and knowledge of the system to physical synthesis by guiding placement to boost performance, reduce power and improve clock management. Other advanced design tool features include support for partitioning of designs among teams and reuse of IP. The following sections discuss in greater detail the difficulties of implementing FPGA by contrasting FPGA with ASIC technologies. The benefits of physical synthesis are shown in the context of understanding the limits of conventional synthesis when applied to an FPGA design. There is also a discussion of pushbutton synthesis verses design planning.

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