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Latest EDA News
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ST-Ericsson selected MVSIM for its proven ability to comprehensively verify low power techniques, including standby and built-in automated low power assertions, which enable the early detection of bugs. The tool's extensive support for the IEEE 1801 [Unified Power Format (UPF)] power format, on which the STw8500 project team has standardized, was also a deciding factor. |
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IEEE-Standard Encryption for SecureIP Models Offers 2X Performance Boost; Open Verification Methodology (OVM) to Increase Schedule Predictability and Quality |
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Synopsys today announced the results of a collaboration with TSMC under TSMC's Unified Design-for-Manufacturing (UDFM) architecture effort. This collaboration enables designers to improve yields and accelerate time to market through more accurate lithography simulation at 28 nanometer (nm) and below. |
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The reference flow, the result of collaboration between Synopsys Professional Services and SMIC, adds the Synopsys Eclypse™ Low Power Solution and IC Compiler Zroute technology, expanding the resources available to designers to address low power and design-for-manufacturing challenges at smaller process nodes. |
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Mentor Graphics today announced that its silicon test and diagnosis suite has been validated by UMC for use in its 65 and 40 nanometer reference flows. The foundation of this comprehensive silicon test flow is the TestKompress® automated test pattern generation (ATPG) solution for achieving high test quality with the lowest test cost. |
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SpringSoft today announced a multi-year technology agreement with TSMC to jointly develop and validate process design kits (PDKs) for leading-edge chip manufacturing technologies. |
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Calypto announced the availability of its PowerPro MG (memory gating) tool. The new tool is the industry’s first product that automatically generates power-optimized RTL by taking advantage of the low-power modes available in today’s leading on-chip memories. |
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Tiempo will reveal at the 46th DAC, its unique and breakthrough asynchronous synthesis tool. ACC (“Asynchronous Circuit Compiler”) is the first synthesis tool on the market which automatically generates asynchronous and delay-insensitive circuits from a model written in a standard hardware description language. |
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Paradigm Works today announced VMM 1.1 enhancements to its SystemVerilog FrameWorks™ VMM Template Generator software. The VMM Template Generator takes user input parameters and automatically creates a functional framework for a VMM-compliant verification environment. |
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Under the terms of the agreement, Actel maintains rights to provide Actel-specific versions of Synopsys' Synplify Pro®, Identify® and Synplify® DSP software as part of the Libero® Integrated Design Environment (IDE). |
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