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Latest EDA News

Cadence Collaborates With ARM to Deliver Hardware/Software Emulation Environment, Accelerating Processor-Based Design (Oct. 07, 2008) Cadence Design Systems announced today the availability of an ARM hardware/software co-verification environment that accelerates the system validation process and provides mutual customers with a faster path to first silicon working with early software.

GateRocket Ships Advanced FPGA Verification Solution for Virtex-5 FPGA (Oct. 02, 2008) The RocketDrive cuts verification and in-system debug time for advanced single or multi-FPGA based projects while adding significant value through seamless integration to a design team’s existing design verification environment, without a change in design flow or verification methodology.

Numetrics Enhances NMX-ERP Software Suite With Extensive Customization Capability (Sep. 24, 2008) Numetrics announced release 3.1 of its NMX-ERP(TM) suite. This version significantly improves user productivity, allowing customization of data entry, project planning models and analysis reports.

OKI Network LSI Reduces Test Time 90% by Combining the Open Verification Methodology (OVM) and Cadence Incisive Technologies (Sep. 24, 2008) OKI Network LSI Co., Ltd., is reporting significant benefits from its use of the Open Verification Methodology (OVM) with Cadence Incisive functional verification technology. Co-developed by Cadence and released last year, the OVM is the first scalable, open, multi-vendor verification methodology for SystemVerilog in the industry.

Infiniscale and Mentor Graphics collaborate with STMicroelectronics to offer a unique design solution for analog parametric yield optimization (Sep. 23, 2008) Infiniscale and Mentor Graphics announced today a collaboration to provide innovative parametric yield optimization to the sub-90nm analog designers’ community, in cooperation with STMicroelectronics, their common major customer.

Domino Logic in ASIC Design Flow - Detailed Methodology and Breakthroughs in High Speed Design Automation Approach (Sep. 22, 2008) Engineers at STMicroelectronic have revealed how to use domino logic, a very fast circuit design style utilized in the highest performance custom designs,in an automated framework.

Synopsys Enters Mixed-Signal Implementation Market With Galaxy Custom Designer (Sep. 22, 2008) Architected for productivity, Galaxy Custom Designer leverages Synopsys' Galaxy™ Design Platform to provide a unified solution for custom and digital designs, thereby enhancing designer efficiency.

New Release of the OVM Takes Verification to the Next Level (Sep. 11, 2008) The new release extends the proven sequential stimulus mechanism in the OVM with transaction-level modeling (TLM) interfaces to improve the modularity and reuse of stimulus sequences. Other enhancements include direct support for parameterized classes in the OVM factory and built-in debug support for TLM connections throughout the hierarchy.

Sequence, Faraday, NemoChips Team To Slash Over 50% Of Total Power From Advanced Mobile Processor Design (Sep. 11, 2008) Pairing Sequence Design's PowerTheater, and the low-power design expertise of NemoChips and Faraday Technology Corporation, led to a 52 percent reduction in total power for an advanced mobile processor design.

Cadence Introduces SaaS Solutions for Semiconductor Design (Sep. 10, 2008) These production-proven, ready-to-go design environments are accessible via the Internet and provide design teams a faster time-to-productivity with reduced risk and cost. Cadence Hosted Design Solutions are available for custom IC design, logic design, physical design, advanced low power, functional verification, and digital implementation.

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