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Latest EDA News

• Oasys Announces RealTime Floorplan Compiler (May. 22, 2013)
  Oasys Design Systems announced the immediate availability of RealTime Floorplan Compiler in the Oasys RealTime suite of physical RTL exploration and synthesis tools. Synthesis engineers, architects and RTL designers can now create a floorplan directly from the RTL that is aware of the designs dataflow and also meets timing, power, area and congestion constraints.
• Cadence Introduces the Tempus Timing Signoff Solution, Delivering Unprecedented Performance and Capacity in Design Closure and Signoff (May. 20, 2013)
  Cadence today introduced the Tempus™ Timing Signoff Solution, a new static timing analysis and closure tool designed to enable SoC developers to speed timing closure and move chip designs to fabrication quickly.
• OneSpin Solutions Reaches for the Cloud, Driving New Technology, Business Model for Easy Adoption (May. 15, 2013)
  OneSpin Solutions today unveiled a new business model based on Cloud Computing designed to give project teams flexibility previously unavailable for electronic design automation (EDA) tools, while eliminating barriers to adoption.
• Forte Design Systems Announces Cynthesizer 5 SystemC High-Level Synthesis (May. 15, 2013)
  Forte Design Systems today unwrapped its enhanced Cynthesizer™ SystemC-based high-level synthesis (HLS) product. The new version includes low power synthesis capabilities, core synthesis algorithms, and a new SystemC integrated development environment (IDE).
• High-Level Synthesis Software from Forte Design Systems Adopted by LG (May. 15, 2013)
  Forte Design Systems today announced that LG Electronics of Seoul, Korea, has adopted Cynthesizer™ SystemC high-level synthesis (HLS) for its next-generation digital television (DTV) design project.
• Jasper Makes Formal Verification Power-Aware with a New Low Power App for Verification of SOCs with Multiple Power Domains (May. 14, 2013)
  Jasper Design Automation has announced the availability of its new JasperGold® Low Power Verification App (JG-LPV App) which enables users to utilize formal methods for the verification of SOC designs optimized for lower power consumption with multiple voltage and power-management domains.
• Achronix Tapes Out Industry's First FinFET-based System-on-Chip Using Synopsys' IC Compiler and IC Validator (May. 13, 2013)
  Synopsys today announced that Achronix Semiconductor has successfully used both Synopsys' IC Compiler™ physical design and IC Validator physical verification solutions to sign off its Speedster22i® FPGA – the industry's first system-on-chip (SoC) design using FinFET transistors.
• Cadence Characterization Solution for Complex Multi-bit Cells Delivers Power and Performance Benefits for Yamaha (May. 13, 2013)
  Cadence today announced that it helped Yamaha Corporation reduce power consumption for its mobile consumer chips with characterization tools that delivered a 10 percent reduction in dynamic power to the clock network required for Yamaha ASICs.
• HiSilicon Technologies Tapes Out 50+ Million Instance ARM Processor-based SoC Using Synopsys IC Compiler (May. 08, 2013)
  Synopsys today announced that HiSilicon has taped out a 50+ million instance ARM® Cortex™-A15 processor based system-on-chip (SoC) using Synopsys' IC Compiler, a key component of Synopsys' Galaxy™ Implementation Platform.
• Cadence Incisive Enterprise Simulator Improves Low-Power Verification Productivity By 30% (May. 07, 2013)
  Cadence today introduced a new version of Incisive® Enterprise Simulator, with features that improve low-power verification productivity of complex SoCs by 30 percent.