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Latest EDA News

• Synopsys Delivers 2X Speedup for Implementing and Verifying Functional ECOs (Jun. 17, 2013)
  Formality Ultra includes innovative matching and verification technologies to efficiently guide designers through the implementation of functional ECOs with minimal impact to the design and verify the correctness of the ECOs in minutes for multimillion instance designs.
• SilabTech's 28nm High-Speed PHYs Delivered Ahead of Schedule with Mentor Graphics Tool Flow (Jun. 11, 2013)
  Mentor Graphics today announced that SilabTech Pvt. Ltd. has achieved first silicon success for their latest 28nm high-speed, mixed-signal PHY IPs for PCI Express, SATA, MIPI, M-PHY and USB 3.0 in advance of the planned schedule.
• Synopsys Unveils New Synthesis-Based Test Technology Delivering Up to 3X Higher Compression (Jun. 11, 2013)
  Synopsys today unveiled a new, innovative test technology to further reduce the cost of testing silicon devices by delivering up to 3x higher test compression and minimizing the time required to test each silicon die.
• Jasper and Duolog Partner to Combine SoC Integration with Formal Verification (Jun. 06, 2013)
  The integrated flows by Duolog and Jasper will enable IP/SoC development teams to deliver qualified, integration-ready IP and SoC assembly that is seamlessly verified using formal verification methods.
• Samplify's APAX Technology Cuts Memory Power Consumption by 59% During Video Playback on Mobile Devices (Jun. 05, 2013)
  Samplify, the leading intellectual property company for accelerating memory, storage, and I/O bottlenecks in mobile devices, consumer electronics, and computing, announces that it has completed testing of its APAX technology with an H.264 decoder to reduce the power consumption of the memory subsystem of mobile devices during video playback.
• Tabula Announces Availability of Stylus Compiler Version 2.6.2 (Jun. 04, 2013)
  Tabula today announced the availability revision 2.6.2 of its Stylus compiler, which supports its ABAX2P1 device and its suite of high-performance Ethernet packet processing solutions. This release marks a new step in Tabula’s ongoing software roadmap execution.
• Cochlear Adopts Target's Optimizing C Compiler Technology for its Ultra-Low Power Hearing Implant DSP (Jun. 04, 2013)
  Target Compiler today announced that Cochlear Ltd. (ASX: COH) has engaged with Target as its supplier of a complete software development kit (SDK) for its NEO ultra-low power digital signal processor (DSP).
• Target Compiler Technologies Expands Architectural Exploration into IP Subsystem Design (Jun. 03, 2013)
  Target Compiler today announced a collection of enhancements and additions to its product line which collectively move the company firmly into the intellectual property (IP) subsystem domain.
• Cadence Design Tools Certified for TSMC 16nm FinFET Process and for TSMC 20nm Process (May. 29, 2013)
  Cadence announced today that several of its system-on-chip development tools have achieved version 0.1 of design rule manual (DRM) and SPICE model tool certification for TSMC’s 16-nanometer FinFET process.
• TSMC Certifies Synopsys' Digital and Custom Solutions for 16-nm FinFET Process (May. 29, 2013)
  Synopsys today announced that TSMC has certified a comprehensive list of custom and digital design tools from Synopsys for 16-nm FinFET process Design Rule Manual (DRM) and SPICE V0.1.