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Cadence Design Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Enterprise Tools, Interoperability Tools, ASIC Layout, Custom Layout, Delay Calculation, DRC, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Lithography, Mask Design, MCM, Hybrid and Packaging Design, Metal - Migration Analysis, PCB CAM, PCB Design, PCB SPICE, PCB Virtual Prototype, Physical Libraries, Power Analysis, Process Migration, RET, Reverse Synthesis, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Compiler, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Power Analysis, ESL Simulation, ESL Test and Verification, DSP, Memory, MEMS, Networking, Telecomms, Wireless, Design IP, Verification IP, Design Services, Training and Consulting, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, Thermal Design, Acceleration and Emulation, DFT Tools, Formal Analysis, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1988 | Size: 5200 employees |
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Synopsys, Inc.
Helping You Design The Chip Inside CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Design Libraries, Interoperability Tools, ASIC Layout, Custom Layout, Delay Calculation, DRC, EMI Analysis, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, Lithography, Mask Design, Physical Libraries, Power Analysis, RET, Signal - Integrity Analysis, T-Cad, Timing Analysis, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Simulation, ESL Test and Verification, Libraries, DSP, Memory, Networking, Telecomms, Wireless, Design IP, Verification IP, IC Foundry, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, DFT Tools, EMI Design, Formal Analysis, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1986 | Size: 5100 employees |
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Denali Software, Inc.
The world leader in chip interface design and verification. CORE COMPETENCY:Enterprise Tools, Interoperability Tools, ESL Co-Verification, ESL Design and Entry, ESL Simulation, ESL Test and Verification, Memory, Design IP, Verification IP, Silicon Virtual Prototype, Verilog Simulation, VHDL Simulation, Timing Design, Intelligent Test Bench Headquarter: United States |
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HOTBENCH.NET
Create your VHDL & Verilog testbench fast CORE COMPETENCY:Acceleration and Emulation, Enterprise Tools, DSP, Memory, Networking, Telecomms, Wireless, Verilog Simulation, VHDL Simulation, Verification, Intelligent Test Bench, RTL Design and Entry Headquarter: India |
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TSSI - Test Systems Strategies, Inc.
Global Innovator of Design-to-Test Software CORE COMPETENCY:Gate Level Simulation, Enterprise Tools, Interoperability Tools, Debugger, Training and Consulting, Verilog Simulation, VHDL Simulation, Verification, DFT Tools, Intelligent Test Bench Headquarter: United States |
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Tata Elxsi
Engineering creativity CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, Schematic Capture, Design Libraries, Interoperability Tools, ASIC Layout, Custom Layout, DRC, EMI Analysis, FPGA/PLD, IC SPICE and SPICE-like Simulation, Library Development Tools, PCB Design, Physical Libraries, Signal - Integrity Analysis, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Test and Verification, Libraries, RTOS, DSP, Networking, Telecomms, Wireless, Design IP, Verification IP, Design Services, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, DFT Tools, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, RTL Design and Entry Headquarter: United States |
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QThink
The Proven Path to First Pass Silicon CORE COMPETENCY:Gate Level Simulation, Gate Level/Transistor Level Design, ASIC Layout, Custom Layout, IC Implementation, IC SPICE and SPICE-like Simulation, Mask Design, Power Analysis, Signal - Integrity Analysis, Timing Analysis, DSP, Memory, MEMS, Networking, Telecomms, Wireless, Design Services, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Formal Analysis, Formal Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1999 |
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Orora Design Technologies
CORE COMPETENCY:Analog Design, Analog Simulation, RF Design and Simulation, IC DFM Tools, IC SPICE and SPICE-like Simulation, Process Migration, Design IP, Synthesis, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation Headquarter: United States |
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Mirabilis Design Inc.
Performance Analysis and Architecture Exploration CORE COMPETENCY:ESL Co-Verification, ESL Design and Entry, ESL Power Analysis, ESL Simulation, ESL Test and Verification, Libraries, Networking, Telecomms, Wireless, HW/SW Co-Verification, Intelligent Test Bench Headquarter: United States |
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JEDA Technologies
System-Driven Verification Automation CORE COMPETENCY:ESL Co-Verification, ESL Test and Verification, Verification IP, Verification, HW/SW Co-Verification, Intelligent Test Bench Headquarter: United States |
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Imperas, Inc.
Multicore Design Simplified! CORE COMPETENCY:Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Power Analysis, ESL Simulation, ESL Test and Verification, Libraries, RTOS, DSP, Memory, Networking, Telecomms, HW/SW Co-Verification, Intelligent Test Bench, RTL Design and Entry Headquarter: United States |
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GiDEL
CORE COMPETENCY:Acceleration and Emulation, FPGA/PLD, ESL Co-Verification, Libraries, DSP, Memory, Networking, Telecomms, Wireless, Design Services, Silicon Virtual Prototype, Verification, Acceleration and Emulation, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation Headquarter: United States |
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Breker Verification Systems
Predictable Path to 100% Verification Plan Coverage CORE COMPETENCY:DSP, Memory, MEMS, Networking, Telecomms, Wireless, Verification IP, Design Services, Training and Consulting, Verilog Simulation, VHDL Simulation, Verification, Intelligent Test Bench, Mixed Language Simulation Headquarter: United States |
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Avery Design Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Verification IP, Verification, Formal Verification, Intelligent Test Bench Headquarter: United States |
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