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ASYGN
Analog System Design CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, MEMS, Wireless, Design Services, Training and Consulting, Verification, Acceleration and Emulation, Mixed Language Simulation, Mixed Signal Simulation Headquarter: France |
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Cadence Design Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Enterprise Tools, Interoperability Tools, ASIC Layout, Custom Layout, Delay Calculation, DRC, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Lithography, Mask Design, MCM, Hybrid and Packaging Design, Metal - Migration Analysis, PCB CAM, PCB Design, PCB SPICE, PCB Virtual Prototype, Physical Libraries, Power Analysis, Process Migration, RET, Reverse Synthesis, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Compiler, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Power Analysis, ESL Simulation, ESL Test and Verification, DSP, Memory, MEMS, Networking, Telecomms, Wireless, Design IP, Verification IP, Design Services, Training and Consulting, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, Thermal Design, Acceleration and Emulation, DFT Tools, Formal Analysis, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1988 | Size: 5200 employees |
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Mentor Graphics Corp.
EDA Technology Leader CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, Custom Layout, Delay Calculation, DRC, EMI Analysis, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, Lithography, Mask Design, MCM, Hybrid and Packaging Design, PCB CAM, PCB Design, PCB SPICE, PCB Virtual Prototype, Physical Libraries, RET, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Simulation, ESL Test and Verification, Libraries, RTOS, DSP, Memory, Networking, Telecomms, Wireless, Design IP, Verification IP, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Verification, Acceleration and Emulation, DFT Tools, EMI Design, Formal Analysis, Formal Verification, HW/SW Co-Verification, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1981 | Size: 4200 employees |
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Synopsys, Inc.
Helping You Design The Chip Inside CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Design Libraries, Interoperability Tools, ASIC Layout, Custom Layout, Delay Calculation, DRC, EMI Analysis, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, Lithography, Mask Design, Physical Libraries, Power Analysis, RET, Signal - Integrity Analysis, T-Cad, Timing Analysis, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Simulation, ESL Test and Verification, Libraries, DSP, Memory, Networking, Telecomms, Wireless, Design IP, Verification IP, IC Foundry, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, DFT Tools, EMI Design, Formal Analysis, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1986 | Size: 5100 employees |
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Dolphin Integration
The Enabler of mixed signal System-on-Chip CORE COMPETENCY:Analog Simulation, Gate Level Simulation, Schematic Capture, IC SPICE and SPICE-like Simulation, PCB SPICE, Power Analysis, MEMS, Verilog Simulation, VHDL Simulation, HW/SW Co-Verification, Mixed Language Simulation, Mixed Signal Simulation, Power Design Headquarter: France | Founded: 1985 |
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Coupling Wave Solutions
CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, ASIC Layout, Custom Layout, EMI Analysis, Extractors, IC Implementation, Library Development Tools, Physical Libraries, Power Analysis, Signal - Integrity Analysis, Networking, Wireless, Verification IP, Verification, Mixed Signal Simulation, Power Design, Signal-Integrity Design Headquarter: France |
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Veritools, Inc.
Debugging Solutions for Verilog, VHDL and SystemVerilog CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, IC SPICE and SPICE-like Simulation, Verilog Simulation, VHDL Simulation, Verification, Mixed Language Simulation, Mixed Signal Simulation, RTL Design and Entry Headquarter: United States | Founded: 1992 | Size: 25 employees |
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True Circuits, Inc.
timing is everything CORE COMPETENCY:Analog Design, Analog Simulation, Design Libraries, Design IP, Timing Design, Mixed Signal Simulation Headquarter: United States |
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Triad Semiconductor, Inc.
Configurable low-cost mixed signal Via-ASIC solutions CORE COMPETENCY:Analog Design, Analog Simulation, Schematic Capture, Design Libraries, IC SPICE and SPICE-like Simulation, Libraries, Design IP, Design Services, Silicon Virtual Prototype, Verilog Simulation, VHDL Simulation, Mixed Language Simulation, Mixed Signal Simulation, RTL Design and Entry Headquarter: United States | Size: 42 employees |
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Tanner EDA
Speeding Concept to Silicon CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, ASIC Layout, Custom Layout, DRC, Extractors, IC SPICE and SPICE-like Simulation, Lithography, Mask Design, MEMS, Verification, Mixed Signal Simulation Headquarter: United States |
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QThink
The Proven Path to First Pass Silicon CORE COMPETENCY:Gate Level Simulation, Gate Level/Transistor Level Design, ASIC Layout, Custom Layout, IC Implementation, IC SPICE and SPICE-like Simulation, Mask Design, Power Analysis, Signal - Integrity Analysis, Timing Analysis, DSP, Memory, MEMS, Networking, Telecomms, Wireless, Design Services, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Formal Analysis, Formal Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1999 |
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Orora Design Technologies
CORE COMPETENCY:Analog Design, Analog Simulation, RF Design and Simulation, IC DFM Tools, IC SPICE and SPICE-like Simulation, Process Migration, Design IP, Synthesis, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation Headquarter: United States |
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OptEM Engineering Inc.
Software and Services for Electronic Interconnect Design, Modeling and Analysis CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Extractors, IC SPICE and SPICE-like Simulation, MCM, Hybrid and Packaging Design, PCB Design, Signal - Integrity Analysis, Timing Analysis, Memory, MEMS, Networking, Telecomms, Wireless, Design Services, Training and Consulting, Verification, Mixed Signal Simulation, Signal-Integrity Design Headquarter: Canada |
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OEA International, Inc.
The Gold Standard for Accurate Parasitic Extraction & Signal Integrity Solutions CORE COMPETENCY:Analog Design, Analog Simulation, RF Design and Simulation, ASIC Layout, Extractors, MCM, Hybrid and Packaging Design, PCB Design, Power Analysis, Signal - Integrity Analysis, Timing Analysis, Synthesis, Timing Design, Mixed Signal Simulation, Power Design, Signal-Integrity Design Headquarter: United States |
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MathWorks, Inc. (The)
CORE COMPETENCY:Gate Level Simulation, RF Design and Simulation, ESL Co-Verification, ESL Design and Entry, ESL Simulation, ESL Test and Verification, DSP, Telecomms, Wireless, Verilog Simulation, VHDL Simulation, Verification, Mixed Language Simulation, Mixed Signal Simulation Headquarter: United States |
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Lynguent, Inc.
CORE COMPETENCY:Analog Design, Analog Simulation, Interoperability Tools, Design IP, Verification IP, Mixed Signal Simulation Headquarter: United States |
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Lorentz Solution
EM Design & Verification for the IC Designer CORE COMPETENCY:RF Design and Simulation, Custom Layout, IC Implementation, Signal - Integrity Analysis, Wireless, Design Services, EMI Design, Mixed Signal Simulation, Signal-Integrity Design Headquarter: United States |
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Legend Design Technology, Inc.
CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Delay Calculation, IC SPICE and SPICE-like Simulation, Library Development Tools, Power Analysis, Signal - Integrity Analysis, Timing Analysis, Memory, Networking, Telecomms, Wireless, Mixed Signal Simulation Headquarter: United States |
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FTL Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Enterprise Tools, Delay Calculation, FPGA/PLD, IC SPICE and SPICE-like Simulation, Power Analysis, Target Compiler, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Logic Synthesis, ESL Simulation, ESL Test and Verification, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Acceleration and Emulation, EMI Design, Formal Verification, HW/SW Co-Verification, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry Headquarter: United States |
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EMA Design Automation, Inc.
CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, ASIC Layout, Custom Layout, Delay Calculation, DRC, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, MCM, Hybrid and Packaging Design, PCB CAM, PCB Design, PCB SPICE, Power Analysis, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, Formal Analysis, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States |
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Berkeley Design Automation, Inc.
CORE COMPETENCY:Mixed Signal Simulation Headquarter: United States |
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Applied Wave Research, Inc.
CORE COMPETENCY:Analog Design, Analog Simulation, RF Design and Simulation, Schematic Capture, Design Libraries, Custom Layout, DRC, EMI Analysis, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, MCM, Hybrid and Packaging Design, PCB Design, PCB SPICE, ESL Simulation, Mixed Signal Simulation, Signal-Integrity Design Headquarter: United States |
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Anasift Technology, Inc.
CORE COMPETENCY:Analog Design, Analog Simulation, Design Services, Mixed Signal Simulation Headquarter: United States |
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