-
Search IP
- Categories
- Featured Products
-
News
- Categories
- Latest News
-
Industry Articles
- Categories
- Featured Articles
- Blogs
Search for EDA Tools.
|
OR EDA Supplier: list your tools for free in this catalog. |
|
|
Cadence Design Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Enterprise Tools, Interoperability Tools, ASIC Layout, Custom Layout, Delay Calculation, DRC, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Lithography, Mask Design, MCM, Hybrid and Packaging Design, Metal - Migration Analysis, PCB CAM, PCB Design, PCB SPICE, PCB Virtual Prototype, Physical Libraries, Power Analysis, Process Migration, RET, Reverse Synthesis, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Compiler, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Power Analysis, ESL Simulation, ESL Test and Verification, DSP, Memory, MEMS, Networking, Telecomms, Wireless, Design IP, Verification IP, Design Services, Training and Consulting, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, Thermal Design, Acceleration and Emulation, DFT Tools, Formal Analysis, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1988 | Size: 5200 employees |
|
Mentor Graphics Corp.
EDA Technology Leader CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, Custom Layout, Delay Calculation, DRC, EMI Analysis, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, Lithography, Mask Design, MCM, Hybrid and Packaging Design, PCB CAM, PCB Design, PCB SPICE, PCB Virtual Prototype, Physical Libraries, RET, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Simulation, ESL Test and Verification, Libraries, RTOS, DSP, Memory, Networking, Telecomms, Wireless, Design IP, Verification IP, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Verification, Acceleration and Emulation, DFT Tools, EMI Design, Formal Analysis, Formal Verification, HW/SW Co-Verification, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1981 | Size: 4200 employees |
|
Synopsys, Inc.
Helping You Design The Chip Inside CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Design Libraries, Interoperability Tools, ASIC Layout, Custom Layout, Delay Calculation, DRC, EMI Analysis, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, Lithography, Mask Design, Physical Libraries, Power Analysis, RET, Signal - Integrity Analysis, T-Cad, Timing Analysis, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Simulation, ESL Test and Verification, Libraries, DSP, Memory, Networking, Telecomms, Wireless, Design IP, Verification IP, IC Foundry, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, DFT Tools, EMI Design, Formal Analysis, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1986 | Size: 5100 employees |
|
Elgris Technologies, Inc.
CORE COMPETENCY:Gate Level/Transistor Level Design, Interoperability Tools, PCB Design, Reverse Synthesis, Verification, RTL Design and Entry Headquarter: USA | Founded: 2005 |
|
Concurrent EDA
Measureably Faster CORE COMPETENCY:Synthesis, Timing Design, Verification, Acceleration and Emulation, RTL Design and Entry Headquarter: USA |
|
HOTBENCH.NET
Create your VHDL & Verilog testbench fast CORE COMPETENCY:Acceleration and Emulation, Enterprise Tools, DSP, Memory, Networking, Telecomms, Wireless, Verilog Simulation, VHDL Simulation, Verification, Intelligent Test Bench, RTL Design and Entry Headquarter: India |
|
Veritools, Inc.
Debugging Solutions for Verilog, VHDL and SystemVerilog CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, IC SPICE and SPICE-like Simulation, Verilog Simulation, VHDL Simulation, Verification, Mixed Language Simulation, Mixed Signal Simulation, RTL Design and Entry Headquarter: United States | Founded: 1992 | Size: 25 employees |
|
Verific Design Automation
CORE COMPETENCY:Synthesis, Verilog Simulation, VHDL Simulation, Verification, Acceleration and Emulation, DFT Tools, Formal Analysis, Formal Verification, Mixed Language Simulation, RTL Design and Entry Headquarter: United States |
|
Triad Semiconductor, Inc.
Configurable low-cost mixed signal Via-ASIC solutions CORE COMPETENCY:Analog Design, Analog Simulation, Schematic Capture, Design Libraries, IC SPICE and SPICE-like Simulation, Libraries, Design IP, Design Services, Silicon Virtual Prototype, Verilog Simulation, VHDL Simulation, Mixed Language Simulation, Mixed Signal Simulation, RTL Design and Entry Headquarter: United States | Size: 42 employees |
|
Tata Elxsi
Engineering creativity CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, Schematic Capture, Design Libraries, Interoperability Tools, ASIC Layout, Custom Layout, DRC, EMI Analysis, FPGA/PLD, IC SPICE and SPICE-like Simulation, Library Development Tools, PCB Design, Physical Libraries, Signal - Integrity Analysis, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Test and Verification, Libraries, RTOS, DSP, Networking, Telecomms, Wireless, Design IP, Verification IP, Design Services, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, DFT Tools, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, RTL Design and Entry Headquarter: United States |
|
Target Compiler Technologies
EDA tools and services to design, verify and program Application-Specific Instruction-set Processors (ASIPs) CORE COMPETENCY:Target Compiler, Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Power Analysis, ESL Simulation, ESL Test and Verification, Libraries, Design IP, Verification IP, Design Services, HW/SW Co-Verification, RTL Design and Entry Headquarter: United States |
|
QThink
The Proven Path to First Pass Silicon CORE COMPETENCY:Gate Level Simulation, Gate Level/Transistor Level Design, ASIC Layout, Custom Layout, IC Implementation, IC SPICE and SPICE-like Simulation, Mask Design, Power Analysis, Signal - Integrity Analysis, Timing Analysis, DSP, Memory, MEMS, Networking, Telecomms, Wireless, Design Services, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Formal Analysis, Formal Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1999 |
|
Micro Magic, Inc.
Fast Silicon Fast CORE COMPETENCY:Analog Design, Gate Level Simulation, Gate Level/Transistor Level Design, Design Libraries, ASIC Layout, Custom Layout, Mask Design, DSP, Memory, Networking, Telecomms, Wireless, Design IP, RTL Design and Entry Headquarter: United States |
|
Javelin Design Automation, Inc.
CORE COMPETENCY:ASIC Layout, IC Implementation, Power Analysis, Timing Analysis, ESL Design and Entry, ESL Power Analysis, DSP, Networking, Telecomms, Wireless, Silicon Virtual Prototype, Timing Design, Power Design, RTL Design and Entry Headquarter: United States |
|
Interra Systems, Inc.
CORE COMPETENCY:ASIC Layout, Extractors, IC SPICE and SPICE-like Simulation, Library Development Tools, Power Analysis, Timing Analysis, ESL Co-Verification, ESL Simulation, ESL Test and Verification, Memory, Design Services, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, Acceleration and Emulation, Formal Analysis, Formal Verification, HW/SW Co-Verification, Mixed Language Simulation, RTL Design and Entry Headquarter: United States |
|
Incentia Design Systems, Inc.
CORE COMPETENCY:Delay Calculation, Power Analysis, Signal - Integrity Analysis, Timing Analysis, DSP, Networking, Telecomms, Wireless, Synthesis, DFT Tools, Power Design, RTL Design and Entry Headquarter: United States |
|
Imperas, Inc.
Multicore Design Simplified! CORE COMPETENCY:Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Power Analysis, ESL Simulation, ESL Test and Verification, Libraries, RTOS, DSP, Memory, Networking, Telecomms, HW/SW Co-Verification, Intelligent Test Bench, RTL Design and Entry Headquarter: United States |
|
IC Manage
Industrial Strength Design Management CORE COMPETENCY:Analog Design, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, Interoperability Tools, ASIC Layout, Custom Layout, IC Implementation, Library Development Tools, ESL Design and Entry, Design IP, Verification IP, RTL Design and Entry Headquarter: United States |
|
FTL Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Enterprise Tools, Delay Calculation, FPGA/PLD, IC SPICE and SPICE-like Simulation, Power Analysis, Target Compiler, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Logic Synthesis, ESL Simulation, ESL Test and Verification, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Acceleration and Emulation, EMI Design, Formal Verification, HW/SW Co-Verification, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry Headquarter: United States |
|
FishTail Design Automation
The Golden Timing Constraints Company CORE COMPETENCY:Synthesis, Timing Design, Formal Analysis, RTL Design and Entry Headquarter: United States |
|
EMA Design Automation, Inc.
CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, ASIC Layout, Custom Layout, Delay Calculation, DRC, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, MCM, Hybrid and Packaging Design, PCB CAM, PCB Design, PCB SPICE, Power Analysis, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, Formal Analysis, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States |
|
Dynalith Systems Co., Ltd.
CORE COMPETENCY:Acceleration and Emulation, Gate Level Simulation, FPGA/PLD, ESL Co-Verification, ESL Simulation, ESL Test and Verification, RTOS, DSP, Networking, Telecomms, Verification IP, Training and Consulting, Silicon Virtual Prototype, Verilog Simulation, VHDL Simulation, Verification, Acceleration and Emulation, HW/SW Co-Verification, RTL Design and Entry Headquarter: South Korea |
|
Concept Engineering GmbH
CORE COMPETENCY:Gate Level/Transistor Level Design, DRC, Signal - Integrity Analysis, Verification, RTL Design and Entry, Signal-Integrity Design Headquarter: Germany |
|
ClioSoft, Inc.
Empowering Global Collaboration and Design Data Management CORE COMPETENCY:Analog Design, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, ASIC Layout, Custom Layout, IC Implementation, Library Development Tools, ESL Design and Entry, Design IP, Verification IP, RTL Design and Entry Headquarter: United States |
|
Bluespec, Inc.
Reinventing Hardware Design(tm) CORE COMPETENCY:ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Power Analysis, ESL Simulation, ESL Test and Verification, Design IP, Verification IP, Design Services, Synthesis, Verification, Acceleration and Emulation, RTL Design and Entry Headquarter: United States |
|
Blue Pearl Software
CORE COMPETENCY:IC Implementation, Timing Analysis, Synthesis, Timing Design, DFT Tools, Formal Analysis, Formal Verification, RTL Design and Entry Headquarter: United States |
|
Axiom Design Automation
Delivering Verification Performance CORE COMPETENCY:Gate Level Simulation, DSP, Design IP, Verification IP, Design Services, Verilog Simulation, Formal Analysis, Formal Verification, Intelligent Test Bench, RTL Design and Entry Headquarter: United States |
|
Atrenta Inc.
Think Early Design Closure! Think Atrenta! CORE COMPETENCY:IC Implementation, Power Analysis, Timing Analysis, ESL Design and Entry, ESL Power Analysis, Verification IP, Silicon Virtual Prototype, DFT Tools, Formal Analysis, Formal Verification, Power Design, RTL Design and Entry Headquarter: United States |
|
Aldec, Inc.
The Design Verification Company CORE COMPETENCY:Acceleration and Emulation, Gate Level Simulation, Schematic Capture, ESL Co-Verification, ESL Design and Entry, ESL Simulation, Design IP, Verilog Simulation, VHDL Simulation, Verification, Acceleration and Emulation, HW/SW Co-Verification, Mixed Language Simulation, RTL Design and Entry Headquarter: United States |
© 2013 Design And Reuse
All Rights Reserved.
No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.
Talk to us
Add your Products