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ASYGN
Analog System Design CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, MEMS, Wireless, Design Services, Training and Consulting, Verification, Acceleration and Emulation, Mixed Language Simulation, Mixed Signal Simulation Headquarter: France |
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Cadence Design Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Enterprise Tools, Interoperability Tools, ASIC Layout, Custom Layout, Delay Calculation, DRC, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Lithography, Mask Design, MCM, Hybrid and Packaging Design, Metal - Migration Analysis, PCB CAM, PCB Design, PCB SPICE, PCB Virtual Prototype, Physical Libraries, Power Analysis, Process Migration, RET, Reverse Synthesis, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Compiler, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Power Analysis, ESL Simulation, ESL Test and Verification, DSP, Memory, MEMS, Networking, Telecomms, Wireless, Design IP, Verification IP, Design Services, Training and Consulting, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, Thermal Design, Acceleration and Emulation, DFT Tools, Formal Analysis, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1988 | Size: 5200 employees |
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Mentor Graphics Corp.
EDA Technology Leader CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, Custom Layout, Delay Calculation, DRC, EMI Analysis, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, Lithography, Mask Design, MCM, Hybrid and Packaging Design, PCB CAM, PCB Design, PCB SPICE, PCB Virtual Prototype, Physical Libraries, RET, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Simulation, ESL Test and Verification, Libraries, RTOS, DSP, Memory, Networking, Telecomms, Wireless, Design IP, Verification IP, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Verification, Acceleration and Emulation, DFT Tools, EMI Design, Formal Analysis, Formal Verification, HW/SW Co-Verification, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1981 | Size: 4200 employees |
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EVE
The Fastest Verification CORE COMPETENCY:Acceleration and Emulation, Gate Level Simulation, ESL Co-Verification, ESL Simulation, ESL Test and Verification, Verification, Acceleration and Emulation, HW/SW Co-Verification Headquarter: United States |
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HOTBENCH.NET
Create your VHDL & Verilog testbench fast CORE COMPETENCY:Acceleration and Emulation, Enterprise Tools, DSP, Memory, Networking, Telecomms, Wireless, Verilog Simulation, VHDL Simulation, Verification, Intelligent Test Bench, RTL Design and Entry Headquarter: India |
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MunEDA GmbH
Design for Yield - Yield is Money! CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, IC DFM Tools, Power Analysis, DSP, Memory, MEMS, Networking, Telecomms, Wireless, Design IP, Design Services, Training and Consulting, Synthesis Headquarter: Germany |
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Liga Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Gate Level Simulation, Interoperability Tools, Design IP, Verification IP, Verilog Simulation, Verification, Acceleration and Emulation, HW/SW Co-Verification Headquarter: United States |
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GiDEL
CORE COMPETENCY:Acceleration and Emulation, FPGA/PLD, ESL Co-Verification, Libraries, DSP, Memory, Networking, Telecomms, Wireless, Design Services, Silicon Virtual Prototype, Verification, Acceleration and Emulation, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation Headquarter: United States |
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FTL Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Enterprise Tools, Delay Calculation, FPGA/PLD, IC SPICE and SPICE-like Simulation, Power Analysis, Target Compiler, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Logic Synthesis, ESL Simulation, ESL Test and Verification, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Acceleration and Emulation, EMI Design, Formal Verification, HW/SW Co-Verification, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry Headquarter: United States |
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Dynalith Systems Co., Ltd.
CORE COMPETENCY:Acceleration and Emulation, Gate Level Simulation, FPGA/PLD, ESL Co-Verification, ESL Simulation, ESL Test and Verification, RTOS, DSP, Networking, Telecomms, Verification IP, Training and Consulting, Silicon Virtual Prototype, Verilog Simulation, VHDL Simulation, Verification, Acceleration and Emulation, HW/SW Co-Verification, RTL Design and Entry Headquarter: South Korea |
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Dini Group (The)
CORE COMPETENCY:Acceleration and Emulation, Gate Level/Transistor Level Design, ESL Simulation, ESL Test and Verification, Design Services, Silicon Virtual Prototype, Acceleration and Emulation Headquarter: United States |
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Avery Design Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Verification IP, Verification, Formal Verification, Intelligent Test Bench Headquarter: United States |
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Aldec, Inc.
The Design Verification Company CORE COMPETENCY:Acceleration and Emulation, Gate Level Simulation, Schematic Capture, ESL Co-Verification, ESL Design and Entry, ESL Simulation, Design IP, Verilog Simulation, VHDL Simulation, Verification, Acceleration and Emulation, HW/SW Co-Verification, Mixed Language Simulation, RTL Design and Entry Headquarter: United States |
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