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ASYGN
Analog System Design CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, MEMS, Wireless, Design Services, Training and Consulting, Verification, Acceleration and Emulation, Mixed Language Simulation, Mixed Signal Simulation Headquarter: France |
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Cadence Design Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Enterprise Tools, Interoperability Tools, ASIC Layout, Custom Layout, Delay Calculation, DRC, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Lithography, Mask Design, MCM, Hybrid and Packaging Design, Metal - Migration Analysis, PCB CAM, PCB Design, PCB SPICE, PCB Virtual Prototype, Physical Libraries, Power Analysis, Process Migration, RET, Reverse Synthesis, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Compiler, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Power Analysis, ESL Simulation, ESL Test and Verification, DSP, Memory, MEMS, Networking, Telecomms, Wireless, Design IP, Verification IP, Design Services, Training and Consulting, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, Thermal Design, Acceleration and Emulation, DFT Tools, Formal Analysis, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1988 | Size: 5200 employees |
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Mentor Graphics Corp.
EDA Technology Leader CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, Custom Layout, Delay Calculation, DRC, EMI Analysis, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, Lithography, Mask Design, MCM, Hybrid and Packaging Design, PCB CAM, PCB Design, PCB SPICE, PCB Virtual Prototype, Physical Libraries, RET, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Simulation, ESL Test and Verification, Libraries, RTOS, DSP, Memory, Networking, Telecomms, Wireless, Design IP, Verification IP, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Verification, Acceleration and Emulation, DFT Tools, EMI Design, Formal Analysis, Formal Verification, HW/SW Co-Verification, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1981 | Size: 4200 employees |
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Synopsys, Inc.
Helping You Design The Chip Inside CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Design Libraries, Interoperability Tools, ASIC Layout, Custom Layout, Delay Calculation, DRC, EMI Analysis, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, Lithography, Mask Design, Physical Libraries, Power Analysis, RET, Signal - Integrity Analysis, T-Cad, Timing Analysis, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Simulation, ESL Test and Verification, Libraries, DSP, Memory, Networking, Telecomms, Wireless, Design IP, Verification IP, IC Foundry, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, DFT Tools, EMI Design, Formal Analysis, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1986 | Size: 5100 employees |
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Coupling Wave Solutions
CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, ASIC Layout, Custom Layout, EMI Analysis, Extractors, IC Implementation, Library Development Tools, Physical Libraries, Power Analysis, Signal - Integrity Analysis, Networking, Wireless, Verification IP, Verification, Mixed Signal Simulation, Power Design, Signal-Integrity Design Headquarter: France |
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Elgris Technologies, Inc.
CORE COMPETENCY:Gate Level/Transistor Level Design, Interoperability Tools, PCB Design, Reverse Synthesis, Verification, RTL Design and Entry Headquarter: USA | Founded: 2005 |
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Veritools, Inc.
Debugging Solutions for Verilog, VHDL and SystemVerilog CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, IC SPICE and SPICE-like Simulation, Verilog Simulation, VHDL Simulation, Verification, Mixed Language Simulation, Mixed Signal Simulation, RTL Design and Entry Headquarter: United States | Founded: 1992 | Size: 25 employees |
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Tata Elxsi
Engineering creativity CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, Schematic Capture, Design Libraries, Interoperability Tools, ASIC Layout, Custom Layout, DRC, EMI Analysis, FPGA/PLD, IC SPICE and SPICE-like Simulation, Library Development Tools, PCB Design, Physical Libraries, Signal - Integrity Analysis, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Test and Verification, Libraries, RTOS, DSP, Networking, Telecomms, Wireless, Design IP, Verification IP, Design Services, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, DFT Tools, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, RTL Design and Entry Headquarter: United States |
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Tanner EDA
Speeding Concept to Silicon CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, ASIC Layout, Custom Layout, DRC, Extractors, IC SPICE and SPICE-like Simulation, Lithography, Mask Design, MEMS, Verification, Mixed Signal Simulation Headquarter: United States |
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Solido Design Automation Inc.
Transistor-Level Statistical Design and Verification tools for Analog/Mixed-Signal, Custom Digital and Memory designers. CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level/Transistor Level Design Headquarter: Canada |
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QThink
The Proven Path to First Pass Silicon CORE COMPETENCY:Gate Level Simulation, Gate Level/Transistor Level Design, ASIC Layout, Custom Layout, IC Implementation, IC SPICE and SPICE-like Simulation, Mask Design, Power Analysis, Signal - Integrity Analysis, Timing Analysis, DSP, Memory, MEMS, Networking, Telecomms, Wireless, Design Services, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Formal Analysis, Formal Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1999 |
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Proficient Design, LLC
CORE COMPETENCY:Gate Level/Transistor Level Design, Power Analysis, Design IP, Training and Consulting, Power Design Headquarter: United States |
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PDF Solutions
CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Design Libraries, DRC, IC DFM Tools, IC Implementation, Library Development Tools, Design Services, Training and Consulting Headquarter: United States |
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OptEM Engineering Inc.
Software and Services for Electronic Interconnect Design, Modeling and Analysis CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Extractors, IC SPICE and SPICE-like Simulation, MCM, Hybrid and Packaging Design, PCB Design, Signal - Integrity Analysis, Timing Analysis, Memory, MEMS, Networking, Telecomms, Wireless, Design Services, Training and Consulting, Verification, Mixed Signal Simulation, Signal-Integrity Design Headquarter: Canada |
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Nangate
Making Simple Things Simple and Complex Things Possible CORE COMPETENCY:Gate Level/Transistor Level Design, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, Physical Libraries, Design Services Headquarter: United States |
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MunEDA GmbH
Design for Yield - Yield is Money! CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, IC DFM Tools, Power Analysis, DSP, Memory, MEMS, Networking, Telecomms, Wireless, Design IP, Design Services, Training and Consulting, Synthesis Headquarter: Germany |
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Micro Magic, Inc.
Fast Silicon Fast CORE COMPETENCY:Analog Design, Gate Level Simulation, Gate Level/Transistor Level Design, Design Libraries, ASIC Layout, Custom Layout, Mask Design, DSP, Memory, Networking, Telecomms, Wireless, Design IP, RTL Design and Entry Headquarter: United States |
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Library Technologies, Inc.
CORE COMPETENCY:Gate Level Simulation, Gate Level/Transistor Level Design, Design Libraries, Delay Calculation, IC Implementation, Library Development Tools, Physical Libraries, Power Analysis, Timing Analysis, Synthesis, Verilog Simulation, Timing Design, Verification, Power Design, Signal-Integrity Design Headquarter: United States |
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Legend Design Technology, Inc.
CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Delay Calculation, IC SPICE and SPICE-like Simulation, Library Development Tools, Power Analysis, Signal - Integrity Analysis, Timing Analysis, Memory, Networking, Telecomms, Wireless, Mixed Signal Simulation Headquarter: United States |
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IC Manage
Industrial Strength Design Management CORE COMPETENCY:Analog Design, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, Interoperability Tools, ASIC Layout, Custom Layout, IC Implementation, Library Development Tools, ESL Design and Entry, Design IP, Verification IP, RTL Design and Entry Headquarter: United States |
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Gradient Design Automation
CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level/Transistor Level Design, ASIC Layout, Custom Layout, IC SPICE and SPICE-like Simulation, Metal - Migration Analysis, Power Analysis, Thermal Analysis, DSP, Networking, Telecomms, Wireless Headquarter: United States |
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FTL Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Enterprise Tools, Delay Calculation, FPGA/PLD, IC SPICE and SPICE-like Simulation, Power Analysis, Target Compiler, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Logic Synthesis, ESL Simulation, ESL Test and Verification, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Acceleration and Emulation, EMI Design, Formal Verification, HW/SW Co-Verification, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry Headquarter: United States |
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EMA Design Automation, Inc.
CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, ASIC Layout, Custom Layout, Delay Calculation, DRC, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, MCM, Hybrid and Packaging Design, PCB CAM, PCB Design, PCB SPICE, Power Analysis, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, Formal Analysis, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States |
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Dini Group (The)
CORE COMPETENCY:Acceleration and Emulation, Gate Level/Transistor Level Design, ESL Simulation, ESL Test and Verification, Design Services, Silicon Virtual Prototype, Acceleration and Emulation Headquarter: United States |
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Concept Engineering GmbH
CORE COMPETENCY:Gate Level/Transistor Level Design, DRC, Signal - Integrity Analysis, Verification, RTL Design and Entry, Signal-Integrity Design Headquarter: Germany |
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ClioSoft, Inc.
Empowering Global Collaboration and Design Data Management CORE COMPETENCY:Analog Design, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, ASIC Layout, Custom Layout, IC Implementation, Library Development Tools, ESL Design and Entry, Design IP, Verification IP, RTL Design and Entry Headquarter: United States |
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Applied Simulation Technology
Advanced Simulation for High Speed Design CORE COMPETENCY:Analog Simulation, Gate Level/Transistor Level Design, Delay Calculation, EMI Analysis, Extractors, IC SPICE and SPICE-like Simulation, PCB SPICE, Power Analysis, Signal - Integrity Analysis, EMI Design, Signal-Integrity Design Headquarter: United States |
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ANSYS
CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, Interoperability Tools, EMI Analysis, Extractors, IC SPICE and SPICE-like Simulation, MCM, Hybrid and Packaging Design, Power Analysis, Signal - Integrity Analysis, Thermal Analysis, Memory, MEMS, Networking, Telecomms, Wireless, Signal-Integrity Design Headquarter: United States |
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Analog Rails
CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Custom Layout, IC Implementation, Mask Design, Process Migration Headquarter: United States |
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Altos Design Automation
Improve your view... CORE COMPETENCY:Gate Level Simulation, Gate Level/Transistor Level Design, Design Libraries, Delay Calculation, IC SPICE and SPICE-like Simulation, Library Development Tools, Physical Libraries, Power Analysis, Signal - Integrity Analysis, Timing Analysis, Verilog Simulation, VHDL Simulation, Timing Design, Power Design, Signal-Integrity Design Headquarter: United States |
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