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Cadence Design Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Enterprise Tools, Interoperability Tools, ASIC Layout, Custom Layout, Delay Calculation, DRC, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Lithography, Mask Design, MCM, Hybrid and Packaging Design, Metal - Migration Analysis, PCB CAM, PCB Design, PCB SPICE, PCB Virtual Prototype, Physical Libraries, Power Analysis, Process Migration, RET, Reverse Synthesis, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Compiler, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Power Analysis, ESL Simulation, ESL Test and Verification, DSP, Memory, MEMS, Networking, Telecomms, Wireless, Design IP, Verification IP, Design Services, Training and Consulting, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, Thermal Design, Acceleration and Emulation, DFT Tools, Formal Analysis, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1988 | Size: 5200 employees |
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Mentor Graphics Corp.
EDA Technology Leader CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, Custom Layout, Delay Calculation, DRC, EMI Analysis, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, Lithography, Mask Design, MCM, Hybrid and Packaging Design, PCB CAM, PCB Design, PCB SPICE, PCB Virtual Prototype, Physical Libraries, RET, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Simulation, ESL Test and Verification, Libraries, RTOS, DSP, Memory, Networking, Telecomms, Wireless, Design IP, Verification IP, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Verification, Acceleration and Emulation, DFT Tools, EMI Design, Formal Analysis, Formal Verification, HW/SW Co-Verification, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1981 | Size: 4200 employees |
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Synopsys, Inc.
Helping You Design The Chip Inside CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Design Libraries, Interoperability Tools, ASIC Layout, Custom Layout, Delay Calculation, DRC, EMI Analysis, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, Lithography, Mask Design, Physical Libraries, Power Analysis, RET, Signal - Integrity Analysis, T-Cad, Timing Analysis, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Simulation, ESL Test and Verification, Libraries, DSP, Memory, Networking, Telecomms, Wireless, Design IP, Verification IP, IC Foundry, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, DFT Tools, EMI Design, Formal Analysis, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1986 | Size: 5100 employees |
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Z Circuit Automation, Inc.
High-Throughput Cell Library Characterization CORE COMPETENCY:Delay Calculation, IC SPICE and SPICE-like Simulation, Library Development Tools, Power Analysis, Signal - Integrity Analysis, Timing Analysis Headquarter: United States |
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Swati Design
Enabling First Time Silicon Success! CORE COMPETENCY:ASIC Layout, Custom Layout, Delay Calculation, DRC, EMI Analysis, IC Implementation, Metal - Migration Analysis, Power Analysis, Process Migration, Signal - Integrity Analysis, Timing Analysis, Wireless, Synthesis, Timing Design, Verification, DFT Tools, Power Design, Signal-Integrity Design Headquarter: United States |
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Library Technologies, Inc.
CORE COMPETENCY:Gate Level Simulation, Gate Level/Transistor Level Design, Design Libraries, Delay Calculation, IC Implementation, Library Development Tools, Physical Libraries, Power Analysis, Timing Analysis, Synthesis, Verilog Simulation, Timing Design, Verification, Power Design, Signal-Integrity Design Headquarter: United States |
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Legend Design Technology, Inc.
CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Delay Calculation, IC SPICE and SPICE-like Simulation, Library Development Tools, Power Analysis, Signal - Integrity Analysis, Timing Analysis, Memory, Networking, Telecomms, Wireless, Mixed Signal Simulation Headquarter: United States |
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Incentia Design Systems, Inc.
CORE COMPETENCY:Delay Calculation, Power Analysis, Signal - Integrity Analysis, Timing Analysis, DSP, Networking, Telecomms, Wireless, Synthesis, DFT Tools, Power Design, RTL Design and Entry Headquarter: United States |
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FTL Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Enterprise Tools, Delay Calculation, FPGA/PLD, IC SPICE and SPICE-like Simulation, Power Analysis, Target Compiler, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Logic Synthesis, ESL Simulation, ESL Test and Verification, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Acceleration and Emulation, EMI Design, Formal Verification, HW/SW Co-Verification, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry Headquarter: United States |
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EMA Design Automation, Inc.
CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, ASIC Layout, Custom Layout, Delay Calculation, DRC, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, MCM, Hybrid and Packaging Design, PCB CAM, PCB Design, PCB SPICE, Power Analysis, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, Formal Analysis, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States |
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EdXact
CORE COMPETENCY:Delay Calculation, Extractors, IC SPICE and SPICE-like Simulation, Power Analysis, Signal - Integrity Analysis, Timing Analysis Headquarter: France |
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ams
CORE COMPETENCY:Design Libraries, ASIC Layout, Custom Layout, Delay Calculation, DRC, Extractors, IC Implementation, IC SPICE and SPICE-like Simulation, Lithography, Mask Design, Physical Libraries, T-Cad, Libraries, DSP, Memory, Design IP Headquarter: United States |
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Applied Simulation Technology
Advanced Simulation for High Speed Design CORE COMPETENCY:Analog Simulation, Gate Level/Transistor Level Design, Delay Calculation, EMI Analysis, Extractors, IC SPICE and SPICE-like Simulation, PCB SPICE, Power Analysis, Signal - Integrity Analysis, EMI Design, Signal-Integrity Design Headquarter: United States |
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Altos Design Automation
Improve your view... CORE COMPETENCY:Gate Level Simulation, Gate Level/Transistor Level Design, Design Libraries, Delay Calculation, IC SPICE and SPICE-like Simulation, Library Development Tools, Physical Libraries, Power Analysis, Signal - Integrity Analysis, Timing Analysis, Verilog Simulation, VHDL Simulation, Timing Design, Power Design, Signal-Integrity Design Headquarter: United States |
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