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OR EDA Supplier: list your tools for free in this catalog. |
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Cadence Design Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Enterprise Tools, Interoperability Tools, ASIC Layout, Custom Layout, Delay Calculation, DRC, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Lithography, Mask Design, MCM, Hybrid and Packaging Design, Metal - Migration Analysis, PCB CAM, PCB Design, PCB SPICE, PCB Virtual Prototype, Physical Libraries, Power Analysis, Process Migration, RET, Reverse Synthesis, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Compiler, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Power Analysis, ESL Simulation, ESL Test and Verification, DSP, Memory, MEMS, Networking, Telecomms, Wireless, Design IP, Verification IP, Design Services, Training and Consulting, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, Thermal Design, Acceleration and Emulation, DFT Tools, Formal Analysis, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1988 | Size: 5200 employees |
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Synopsys, Inc.
Helping You Design The Chip Inside CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Design Libraries, Interoperability Tools, ASIC Layout, Custom Layout, Delay Calculation, DRC, EMI Analysis, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, Lithography, Mask Design, Physical Libraries, Power Analysis, RET, Signal - Integrity Analysis, T-Cad, Timing Analysis, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Simulation, ESL Test and Verification, Libraries, DSP, Memory, Networking, Telecomms, Wireless, Design IP, Verification IP, IC Foundry, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, DFT Tools, EMI Design, Formal Analysis, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1986 | Size: 5100 employees |
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Dolphin Integration
The Enabler of mixed signal System-on-Chip CORE COMPETENCY:Analog Simulation, Gate Level Simulation, Schematic Capture, IC SPICE and SPICE-like Simulation, PCB SPICE, Power Analysis, MEMS, Verilog Simulation, VHDL Simulation, HW/SW Co-Verification, Mixed Language Simulation, Mixed Signal Simulation, Power Design Headquarter: France | Founded: 1985 |
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Coupling Wave Solutions
CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, ASIC Layout, Custom Layout, EMI Analysis, Extractors, IC Implementation, Library Development Tools, Physical Libraries, Power Analysis, Signal - Integrity Analysis, Networking, Wireless, Verification IP, Verification, Mixed Signal Simulation, Power Design, Signal-Integrity Design Headquarter: France |
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Z Circuit Automation, Inc.
High-Throughput Cell Library Characterization CORE COMPETENCY:Delay Calculation, IC SPICE and SPICE-like Simulation, Library Development Tools, Power Analysis, Signal - Integrity Analysis, Timing Analysis Headquarter: United States |
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Swati Design
Enabling First Time Silicon Success! CORE COMPETENCY:ASIC Layout, Custom Layout, Delay Calculation, DRC, EMI Analysis, IC Implementation, Metal - Migration Analysis, Power Analysis, Process Migration, Signal - Integrity Analysis, Timing Analysis, Wireless, Synthesis, Timing Design, Verification, DFT Tools, Power Design, Signal-Integrity Design Headquarter: United States |
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Sigrity, Inc.
Achieve What Others Can't CORE COMPETENCY:EMI Analysis, Extractors, IC Implementation, IC SPICE and SPICE-like Simulation, MCM, Hybrid and Packaging Design, PCB Design, PCB SPICE, Power Analysis, Signal - Integrity Analysis, Training and Consulting, Power Design, Signal-Integrity Design Headquarter: United States |
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QThink
The Proven Path to First Pass Silicon CORE COMPETENCY:Gate Level Simulation, Gate Level/Transistor Level Design, ASIC Layout, Custom Layout, IC Implementation, IC SPICE and SPICE-like Simulation, Mask Design, Power Analysis, Signal - Integrity Analysis, Timing Analysis, DSP, Memory, MEMS, Networking, Telecomms, Wireless, Design Services, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Formal Analysis, Formal Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1999 |
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Prolific, Inc.
CORE COMPETENCY:Library Development Tools, Physical Libraries, Power Analysis, Process Migration, Signal - Integrity Analysis, Timing Analysis Headquarter: United States |
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Proficient Design, LLC
CORE COMPETENCY:Gate Level/Transistor Level Design, Power Analysis, Design IP, Training and Consulting, Power Design Headquarter: United States |
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Nimbic (formerly Physware)
CORE COMPETENCY:RF Design and Simulation, EMI Analysis, Extractors, MCM, Hybrid and Packaging Design, PCB Design, Power Analysis, Signal - Integrity Analysis Headquarter: United States |
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OEA International, Inc.
The Gold Standard for Accurate Parasitic Extraction & Signal Integrity Solutions CORE COMPETENCY:Analog Design, Analog Simulation, RF Design and Simulation, ASIC Layout, Extractors, MCM, Hybrid and Packaging Design, PCB Design, Power Analysis, Signal - Integrity Analysis, Timing Analysis, Synthesis, Timing Design, Mixed Signal Simulation, Power Design, Signal-Integrity Design Headquarter: United States |
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MunEDA GmbH
Design for Yield - Yield is Money! CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, IC DFM Tools, Power Analysis, DSP, Memory, MEMS, Networking, Telecomms, Wireless, Design IP, Design Services, Training and Consulting, Synthesis Headquarter: Germany |
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Library Technologies, Inc.
CORE COMPETENCY:Gate Level Simulation, Gate Level/Transistor Level Design, Design Libraries, Delay Calculation, IC Implementation, Library Development Tools, Physical Libraries, Power Analysis, Timing Analysis, Synthesis, Verilog Simulation, Timing Design, Verification, Power Design, Signal-Integrity Design Headquarter: United States |
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Legend Design Technology, Inc.
CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Delay Calculation, IC SPICE and SPICE-like Simulation, Library Development Tools, Power Analysis, Signal - Integrity Analysis, Timing Analysis, Memory, Networking, Telecomms, Wireless, Mixed Signal Simulation Headquarter: United States |
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Javelin Design Automation, Inc.
CORE COMPETENCY:ASIC Layout, IC Implementation, Power Analysis, Timing Analysis, ESL Design and Entry, ESL Power Analysis, DSP, Networking, Telecomms, Wireless, Silicon Virtual Prototype, Timing Design, Power Design, RTL Design and Entry Headquarter: United States |
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Interra Systems, Inc.
CORE COMPETENCY:ASIC Layout, Extractors, IC SPICE and SPICE-like Simulation, Library Development Tools, Power Analysis, Timing Analysis, ESL Co-Verification, ESL Simulation, ESL Test and Verification, Memory, Design Services, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, Acceleration and Emulation, Formal Analysis, Formal Verification, HW/SW Co-Verification, Mixed Language Simulation, RTL Design and Entry Headquarter: United States |
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Incentia Design Systems, Inc.
CORE COMPETENCY:Delay Calculation, Power Analysis, Signal - Integrity Analysis, Timing Analysis, DSP, Networking, Telecomms, Wireless, Synthesis, DFT Tools, Power Design, RTL Design and Entry Headquarter: United States |
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Gradient Design Automation
CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level/Transistor Level Design, ASIC Layout, Custom Layout, IC SPICE and SPICE-like Simulation, Metal - Migration Analysis, Power Analysis, Thermal Analysis, DSP, Networking, Telecomms, Wireless Headquarter: United States |
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FTL Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Enterprise Tools, Delay Calculation, FPGA/PLD, IC SPICE and SPICE-like Simulation, Power Analysis, Target Compiler, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Logic Synthesis, ESL Simulation, ESL Test and Verification, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Acceleration and Emulation, EMI Design, Formal Verification, HW/SW Co-Verification, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry Headquarter: United States |
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Entasys Design, Inc.
CORE COMPETENCY:Power Analysis, Signal - Integrity Analysis, ESL Design and Entry, ESL Power Analysis, Silicon Virtual Prototype, Signal-Integrity Design Headquarter: South Korea |
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EMA Design Automation, Inc.
CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, ASIC Layout, Custom Layout, Delay Calculation, DRC, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, MCM, Hybrid and Packaging Design, PCB CAM, PCB Design, PCB SPICE, Power Analysis, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, Formal Analysis, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States |
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EdXact
CORE COMPETENCY:Delay Calculation, Extractors, IC SPICE and SPICE-like Simulation, Power Analysis, Signal - Integrity Analysis, Timing Analysis Headquarter: France |
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ChipVision Design Systems
CORE COMPETENCY:Power Analysis, ESL Design and Entry, ESL Power Analysis, DSP, Networking, Telecomms, Wireless Headquarter: Germany |
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Calypto Design Systems
Bridging System and RTL CORE COMPETENCY:ASIC Layout, IC Implementation, Power Analysis, Debugger, ESL Test and Verification, Temporal Analysis, DSP, Networking, Telecomms, Wireless, Verification IP, Verification, Formal Verification Headquarter: United States |
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Atrenta Inc.
Think Early Design Closure! Think Atrenta! CORE COMPETENCY:IC Implementation, Power Analysis, Timing Analysis, ESL Design and Entry, ESL Power Analysis, Verification IP, Silicon Virtual Prototype, DFT Tools, Formal Analysis, Formal Verification, Power Design, RTL Design and Entry Headquarter: United States |
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Applied Simulation Technology
Advanced Simulation for High Speed Design CORE COMPETENCY:Analog Simulation, Gate Level/Transistor Level Design, Delay Calculation, EMI Analysis, Extractors, IC SPICE and SPICE-like Simulation, PCB SPICE, Power Analysis, Signal - Integrity Analysis, EMI Design, Signal-Integrity Design Headquarter: United States |
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Apache Design Solutions, Inc.
SoC Power and Noise Integrity CORE COMPETENCY:IC SPICE and SPICE-like Simulation, Power Analysis, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis Headquarter: United States |
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ANSYS
CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, Interoperability Tools, EMI Analysis, Extractors, IC SPICE and SPICE-like Simulation, MCM, Hybrid and Packaging Design, Power Analysis, Signal - Integrity Analysis, Thermal Analysis, Memory, MEMS, Networking, Telecomms, Wireless, Signal-Integrity Design Headquarter: United States |
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Altos Design Automation
Improve your view... CORE COMPETENCY:Gate Level Simulation, Gate Level/Transistor Level Design, Design Libraries, Delay Calculation, IC SPICE and SPICE-like Simulation, Library Development Tools, Physical Libraries, Power Analysis, Signal - Integrity Analysis, Timing Analysis, Verilog Simulation, VHDL Simulation, Timing Design, Power Design, Signal-Integrity Design Headquarter: United States |
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