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Mentor Graphics Corp.
EDA Technology Leader CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, Custom Layout, Delay Calculation, DRC, EMI Analysis, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, Lithography, Mask Design, MCM, Hybrid and Packaging Design, PCB CAM, PCB Design, PCB SPICE, PCB Virtual Prototype, Physical Libraries, RET, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Simulation, ESL Test and Verification, Libraries, RTOS, DSP, Memory, Networking, Telecomms, Wireless, Design IP, Verification IP, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Verification, Acceleration and Emulation, DFT Tools, EMI Design, Formal Analysis, Formal Verification, HW/SW Co-Verification, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1981 | Size: 4200 employees |
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Synopsys, Inc.
Helping You Design The Chip Inside CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Design Libraries, Interoperability Tools, ASIC Layout, Custom Layout, Delay Calculation, DRC, EMI Analysis, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, Lithography, Mask Design, Physical Libraries, Power Analysis, RET, Signal - Integrity Analysis, T-Cad, Timing Analysis, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Simulation, ESL Test and Verification, Libraries, DSP, Memory, Networking, Telecomms, Wireless, Design IP, Verification IP, IC Foundry, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, DFT Tools, EMI Design, Formal Analysis, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1986 | Size: 5100 employees |
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Raisonance
CORE COMPETENCY:Interoperability Tools, Compiler, Debugger, ESL Simulation, ESL Test and Verification, Libraries, RTOS, Wireless, Design Services Headquarter: France | Founded: 1988 | Size: 15 employees |
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Virage Logic Corp.
Accelerating Silicon Success CORE COMPETENCY:Design Libraries, IC DFM Tools, Library Development Tools, Physical Libraries, Compiler, Debugger, Libraries, Memory, Networking, Telecomms, Wireless, Design IP, DFT Tools Headquarter: United States |
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TSSI - Test Systems Strategies, Inc.
Global Innovator of Design-to-Test Software CORE COMPETENCY:Gate Level Simulation, Enterprise Tools, Interoperability Tools, Debugger, Training and Consulting, Verilog Simulation, VHDL Simulation, Verification, DFT Tools, Intelligent Test Bench Headquarter: United States |
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Temento Systems
CORE COMPETENCY:Debugger, Verification IP, Training and Consulting, Verification, Acceleration and Emulation, DFT Tools, HW/SW Co-Verification Headquarter: France |
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Tata Elxsi
Engineering creativity CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, Schematic Capture, Design Libraries, Interoperability Tools, ASIC Layout, Custom Layout, DRC, EMI Analysis, FPGA/PLD, IC SPICE and SPICE-like Simulation, Library Development Tools, PCB Design, Physical Libraries, Signal - Integrity Analysis, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Test and Verification, Libraries, RTOS, DSP, Networking, Telecomms, Wireless, Design IP, Verification IP, Design Services, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, DFT Tools, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, RTL Design and Entry Headquarter: United States |
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Target Compiler Technologies
EDA tools and services to design, verify and program Application-Specific Instruction-set Processors (ASIPs) CORE COMPETENCY:Target Compiler, Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Power Analysis, ESL Simulation, ESL Test and Verification, Libraries, Design IP, Verification IP, Design Services, HW/SW Co-Verification, RTL Design and Entry Headquarter: United States |
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Space Codesign
CORE COMPETENCY:Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Simulation, ESL Test and Verification, Libraries, RTOS, Temporal Analysis, Design Services, Training and Consulting Headquarter: Canada |
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Intellitech Corp.
The Technology Leader in Scan Based Debug, Configuration and Test CORE COMPETENCY:FPGA/PLD, MCM, Hybrid and Packaging Design, PCB Design, Debugger, ESL Test and Verification, DSP, Memory, Networking, Telecomms, Wireless, Design IP, Verification IP, Design Services, DFT Tools Headquarter: United States | Founded: 1988 |
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Imperas, Inc.
Multicore Design Simplified! CORE COMPETENCY:Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Power Analysis, ESL Simulation, ESL Test and Verification, Libraries, RTOS, DSP, Memory, Networking, Telecomms, HW/SW Co-Verification, Intelligent Test Bench, RTL Design and Entry Headquarter: United States |
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Gaisler Research AB
CORE COMPETENCY:Compiler, Debugger, ESL Design and Entry, ESL Simulation, Libraries, RTOS, Design IP, Design Services, Training and Consulting Headquarter: Sweden |
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FTL Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Enterprise Tools, Delay Calculation, FPGA/PLD, IC SPICE and SPICE-like Simulation, Power Analysis, Target Compiler, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Logic Synthesis, ESL Simulation, ESL Test and Verification, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Acceleration and Emulation, EMI Design, Formal Verification, HW/SW Co-Verification, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry Headquarter: United States |
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Carbon Design Systems, Inc.
Software Before Silicon CORE COMPETENCY:Debugger, ESL Co-Verification, ESL Simulation, Networking, Telecomms, Wireless, Design IP, Verification IP, Verilog Simulation, VHDL Simulation, Acceleration and Emulation, HW/SW Co-Verification, Mixed Language Simulation Headquarter: United States | Founded: 2002 | Size: 35 employees |
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Calypto Design Systems
Bridging System and RTL CORE COMPETENCY:ASIC Layout, IC Implementation, Power Analysis, Debugger, ESL Test and Verification, Temporal Analysis, DSP, Networking, Telecomms, Wireless, Verification IP, Verification, Formal Verification Headquarter: United States |
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ARM
THE ARCHITECTURE FOR THE DIGITAL WORLD CORE COMPETENCY:Physical Libraries, Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Simulation, ESL Test and Verification, Design IP, Verification IP Headquarter: United States |
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