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OR EDA Supplier: list your tools for free in this catalog. |
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Cadence Design Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Enterprise Tools, Interoperability Tools, ASIC Layout, Custom Layout, Delay Calculation, DRC, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Lithography, Mask Design, MCM, Hybrid and Packaging Design, Metal - Migration Analysis, PCB CAM, PCB Design, PCB SPICE, PCB Virtual Prototype, Physical Libraries, Power Analysis, Process Migration, RET, Reverse Synthesis, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Compiler, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Power Analysis, ESL Simulation, ESL Test and Verification, DSP, Memory, MEMS, Networking, Telecomms, Wireless, Design IP, Verification IP, Design Services, Training and Consulting, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, Thermal Design, Acceleration and Emulation, DFT Tools, Formal Analysis, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1988 | Size: 5200 employees |
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Mentor Graphics Corp.
EDA Technology Leader CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, Custom Layout, Delay Calculation, DRC, EMI Analysis, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, Lithography, Mask Design, MCM, Hybrid and Packaging Design, PCB CAM, PCB Design, PCB SPICE, PCB Virtual Prototype, Physical Libraries, RET, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Simulation, ESL Test and Verification, Libraries, RTOS, DSP, Memory, Networking, Telecomms, Wireless, Design IP, Verification IP, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Verification, Acceleration and Emulation, DFT Tools, EMI Design, Formal Analysis, Formal Verification, HW/SW Co-Verification, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1981 | Size: 4200 employees |
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Synopsys, Inc.
Helping You Design The Chip Inside CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Design Libraries, Interoperability Tools, ASIC Layout, Custom Layout, Delay Calculation, DRC, EMI Analysis, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, Lithography, Mask Design, Physical Libraries, Power Analysis, RET, Signal - Integrity Analysis, T-Cad, Timing Analysis, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Simulation, ESL Test and Verification, Libraries, DSP, Memory, Networking, Telecomms, Wireless, Design IP, Verification IP, IC Foundry, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, DFT Tools, EMI Design, Formal Analysis, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1986 | Size: 5100 employees |
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Denali Software, Inc.
The world leader in chip interface design and verification. CORE COMPETENCY:Enterprise Tools, Interoperability Tools, ESL Co-Verification, ESL Design and Entry, ESL Simulation, ESL Test and Verification, Memory, Design IP, Verification IP, Silicon Virtual Prototype, Verilog Simulation, VHDL Simulation, Timing Design, Intelligent Test Bench Headquarter: United States |
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Synflow SAS
Rediscover hardware design CORE COMPETENCY:ESL Design and Entry, ESL Test and Verification, Design Services, Training and Consulting, RTL Design and Entry Headquarter: France | Founded: 2013 | Size: 2 employees |
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Agnisys Inc.
A project for you a priority for us. CORE COMPETENCY:ESL Design and Entry, ESL Test and Verification Headquarter: USA | Founded: 2003 | Size: 10 employees |
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Scarlet Code LTD
Automate the creation of IP-XACT CORE COMPETENCY:Interoperability Tools, ESL Design and Entry, Design IP, Design Services, HW/SW Co-Verification Headquarter: Essex | Founded: 2005 | Size: 4 employees |
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Dyumnin Technologies
CORE COMPETENCY:ESL Design and Entry, Libraries, Design Services Headquarter: India | Founded: 2002 | Size: 7 employees |
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Tata Elxsi
Engineering creativity CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, Schematic Capture, Design Libraries, Interoperability Tools, ASIC Layout, Custom Layout, DRC, EMI Analysis, FPGA/PLD, IC SPICE and SPICE-like Simulation, Library Development Tools, PCB Design, Physical Libraries, Signal - Integrity Analysis, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Test and Verification, Libraries, RTOS, DSP, Networking, Telecomms, Wireless, Design IP, Verification IP, Design Services, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, DFT Tools, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, RTL Design and Entry Headquarter: United States |
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Target Compiler Technologies
EDA tools and services to design, verify and program Application-Specific Instruction-set Processors (ASIPs) CORE COMPETENCY:Target Compiler, Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Power Analysis, ESL Simulation, ESL Test and Verification, Libraries, Design IP, Verification IP, Design Services, HW/SW Co-Verification, RTL Design and Entry Headquarter: United States |
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Space Codesign
CORE COMPETENCY:Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Simulation, ESL Test and Verification, Libraries, RTOS, Temporal Analysis, Design Services, Training and Consulting Headquarter: Canada |
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Mirabilis Design Inc.
Performance Analysis and Architecture Exploration CORE COMPETENCY:ESL Co-Verification, ESL Design and Entry, ESL Power Analysis, ESL Simulation, ESL Test and Verification, Libraries, Networking, Telecomms, Wireless, HW/SW Co-Verification, Intelligent Test Bench Headquarter: United States |
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MathWorks, Inc. (The)
CORE COMPETENCY:Gate Level Simulation, RF Design and Simulation, ESL Co-Verification, ESL Design and Entry, ESL Simulation, ESL Test and Verification, DSP, Telecomms, Wireless, Verilog Simulation, VHDL Simulation, Verification, Mixed Language Simulation, Mixed Signal Simulation Headquarter: United States |
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Javelin Design Automation, Inc.
CORE COMPETENCY:ASIC Layout, IC Implementation, Power Analysis, Timing Analysis, ESL Design and Entry, ESL Power Analysis, DSP, Networking, Telecomms, Wireless, Silicon Virtual Prototype, Timing Design, Power Design, RTL Design and Entry Headquarter: United States |
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Imperas, Inc.
Multicore Design Simplified! CORE COMPETENCY:Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Power Analysis, ESL Simulation, ESL Test and Verification, Libraries, RTOS, DSP, Memory, Networking, Telecomms, HW/SW Co-Verification, Intelligent Test Bench, RTL Design and Entry Headquarter: United States |
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IC Manage
Industrial Strength Design Management CORE COMPETENCY:Analog Design, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, Interoperability Tools, ASIC Layout, Custom Layout, IC Implementation, Library Development Tools, ESL Design and Entry, Design IP, Verification IP, RTL Design and Entry Headquarter: United States |
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Gaisler Research AB
CORE COMPETENCY:Compiler, Debugger, ESL Design and Entry, ESL Simulation, Libraries, RTOS, Design IP, Design Services, Training and Consulting Headquarter: Sweden |
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Forte Design Systems
CORE COMPETENCY:ESL Design and Entry, ESL Logic Synthesis, ESL Power Analysis, ESL Simulation, ESL Test and Verification, Synthesis Headquarter: United States |
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Entasys Design, Inc.
CORE COMPETENCY:Power Analysis, Signal - Integrity Analysis, ESL Design and Entry, ESL Power Analysis, Silicon Virtual Prototype, Signal-Integrity Design Headquarter: South Korea |
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CoFluent Design
Get fluent in co-design CORE COMPETENCY:ESL Co-Verification, ESL Design and Entry, ESL Power Analysis, ESL Simulation, ESL Test and Verification, Temporal Analysis, Networking, Telecomms, Wireless Headquarter: France |
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ClioSoft, Inc.
Empowering Global Collaboration and Design Data Management CORE COMPETENCY:Analog Design, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, ASIC Layout, Custom Layout, IC Implementation, Library Development Tools, ESL Design and Entry, Design IP, Verification IP, RTL Design and Entry Headquarter: United States |
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ChipVision Design Systems
CORE COMPETENCY:Power Analysis, ESL Design and Entry, ESL Power Analysis, DSP, Networking, Telecomms, Wireless Headquarter: Germany |
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Center for Embedded Computer Systems
Promoting Creativity and Pursuing Discovery CORE COMPETENCY:ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Simulation, ESL Test and Verification Headquarter: United States |
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Bluespec, Inc.
Reinventing Hardware Design(tm) CORE COMPETENCY:ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Power Analysis, ESL Simulation, ESL Test and Verification, Design IP, Verification IP, Design Services, Synthesis, Verification, Acceleration and Emulation, RTL Design and Entry Headquarter: United States |
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Atrenta Inc.
Think Early Design Closure! Think Atrenta! CORE COMPETENCY:IC Implementation, Power Analysis, Timing Analysis, ESL Design and Entry, ESL Power Analysis, Verification IP, Silicon Virtual Prototype, DFT Tools, Formal Analysis, Formal Verification, Power Design, RTL Design and Entry Headquarter: United States |
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ARM
THE ARCHITECTURE FOR THE DIGITAL WORLD CORE COMPETENCY:Physical Libraries, Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Simulation, ESL Test and Verification, Design IP, Verification IP Headquarter: United States |
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Aldec, Inc.
The Design Verification Company CORE COMPETENCY:Acceleration and Emulation, Gate Level Simulation, Schematic Capture, ESL Co-Verification, ESL Design and Entry, ESL Simulation, Design IP, Verilog Simulation, VHDL Simulation, Verification, Acceleration and Emulation, HW/SW Co-Verification, Mixed Language Simulation, RTL Design and Entry Headquarter: United States |
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Agilent Technologies
CORE COMPETENCY:RF Design and Simulation, Design Libraries, Signal - Integrity Analysis, ESL Design and Entry, Telecomms, Wireless, IC Foundry, Training and Consulting Headquarter: United States |
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ACE Associated Compiler Experts bv
Products and services for professional compiler development CORE COMPETENCY:Compiler, ESL Co-Verification, ESL Design and Entry, ESL Test and Verification, DSP, Networking, Telecomms Headquarter: Netherlands |
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