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MIPI DPHY Gen2 Rx-Only 4 Lanes - TSMC 28HPC, HPM, LP 1.8V, North/South Poly Orientation
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22 Supplier(s) Found
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Design and Reuse
The Catalyst of Collaborative IP Based SoC Design CORE COMPETENCY:Enterprise Tools, Design IP, Verification IP, Design Services, Training and Consulting Headquarter: France | Founded: 1997 | Size: 15 employees |
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Cadence Design Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Enterprise Tools, Interoperability Tools, ASIC Layout, Custom Layout, Delay Calculation, DRC, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Lithography, Mask Design, MCM, Hybrid and Packaging Design, Metal - Migration Analysis, PCB CAM, PCB Design, PCB SPICE, PCB Virtual Prototype, Physical Libraries, Power Analysis, Process Migration, RET, Reverse Synthesis, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Compiler, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Power Analysis, ESL Simulation, ESL Test and Verification, DSP, Memory, MEMS, Networking, Telecomms, Wireless, Design IP, Verification IP, Design Services, Training and Consulting, Silicon Virtual Prototype, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, Thermal Design, Acceleration and Emulation, DFT Tools, Formal Analysis, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1988 | Size: 5200 employees |
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Mentor Graphics Corp.
EDA Technology Leader CORE COMPETENCY:Acceleration and Emulation, Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, Custom Layout, Delay Calculation, DRC, EMI Analysis, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, Lithography, Mask Design, MCM, Hybrid and Packaging Design, PCB CAM, PCB Design, PCB SPICE, PCB Virtual Prototype, Physical Libraries, RET, Signal - Integrity Analysis, Thermal Analysis, Timing Analysis, Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Simulation, ESL Test and Verification, Libraries, RTOS, DSP, Memory, Networking, Telecomms, Wireless, Design IP, Verification IP, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Verification, Acceleration and Emulation, DFT Tools, EMI Design, Formal Analysis, Formal Verification, HW/SW Co-Verification, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1981 | Size: 4200 employees |
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Synopsys, Inc.
Helping You Design The Chip Inside CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, Design Libraries, Interoperability Tools, ASIC Layout, Custom Layout, Delay Calculation, DRC, EMI Analysis, Extractors, FPGA/PLD, IC DFM Tools, IC Implementation, IC SPICE and SPICE-like Simulation, Library Development Tools, Lithography, Mask Design, Physical Libraries, Power Analysis, RET, Signal - Integrity Analysis, T-Cad, Timing Analysis, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Simulation, ESL Test and Verification, Libraries, DSP, Memory, Networking, Telecomms, Wireless, Design IP, Verification IP, IC Foundry, Training and Consulting, Synthesis, Verilog Simulation, VHDL Simulation, Timing Design, Verification, DFT Tools, EMI Design, Formal Analysis, Formal Verification, HW/SW Co-Verification, Intelligent Test Bench, Mixed Language Simulation, Mixed Signal Simulation, Power Design, RTL Design and Entry, Signal-Integrity Design Headquarter: United States | Founded: 1986 | Size: 5100 employees |
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Arasan Chip Systems
The Bus Stops Here CORE COMPETENCY:ASIC Layout, Networking, Telecomms, Wireless, Design IP, Verification IP, Design Services, HW/SW Co-Verification Headquarter: United States |
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Denali Software, Inc.
The world leader in chip interface design and verification. CORE COMPETENCY:Enterprise Tools, Interoperability Tools, ESL Co-Verification, ESL Design and Entry, ESL Simulation, ESL Test and Verification, Memory, Design IP, Verification IP, Silicon Virtual Prototype, Verilog Simulation, VHDL Simulation, Timing Design, Intelligent Test Bench Headquarter: United States |
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Coupling Wave Solutions
CORE COMPETENCY:Analog Design, Analog Simulation, Gate Level Simulation, Gate Level/Transistor Level Design, RF Design and Simulation, ASIC Layout, Custom Layout, EMI Analysis, Extractors, IC Implementation, Library Development Tools, Physical Libraries, Power Analysis, Signal - Integrity Analysis, Networking, Wireless, Verification IP, Verification, Mixed Signal Simulation, Power Design, Signal-Integrity Design Headquarter: France |
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Temento Systems
CORE COMPETENCY:Debugger, Verification IP, Training and Consulting, Verification, Acceleration and Emulation, DFT Tools, HW/SW Co-Verification Headquarter: France |
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Quik-Pak
IC Packages, Assembly & Prototype Services CORE COMPETENCY:MEMS, Telecomms, Wireless, Verification IP, IC Foundry, Verification Headquarter: United States |
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OneSpin Solutions GmbH
CORE COMPETENCY:Design IP, Verification IP, Formal Verification Headquarter: Germany |
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Lynguent, Inc.
CORE COMPETENCY:Analog Design, Analog Simulation, Interoperability Tools, Design IP, Verification IP, Mixed Signal Simulation Headquarter: United States |
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Liga Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Gate Level Simulation, Interoperability Tools, Design IP, Verification IP, Verilog Simulation, Verification, Acceleration and Emulation, HW/SW Co-Verification Headquarter: United States |
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Kilopass Technology, Inc.
Scalable NVM Technology in Standard CMOS CORE COMPETENCY:Memory, Design IP, Verification IP Headquarter: United States |
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JEDA Technologies
System-Driven Verification Automation CORE COMPETENCY:ESL Co-Verification, ESL Test and Verification, Verification IP, Verification, HW/SW Co-Verification, Intelligent Test Bench Headquarter: United States |
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Intellitech Corp.
The Technology Leader in Scan Based Debug, Configuration and Test CORE COMPETENCY:FPGA/PLD, MCM, Hybrid and Packaging Design, PCB Design, Debugger, ESL Test and Verification, DSP, Memory, Networking, Telecomms, Wireless, Design IP, Verification IP, Design Services, DFT Tools Headquarter: United States | Founded: 1988 |
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IC Manage
Industrial Strength Design Management CORE COMPETENCY:Analog Design, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, Interoperability Tools, ASIC Layout, Custom Layout, IC Implementation, Library Development Tools, ESL Design and Entry, Design IP, Verification IP, RTL Design and Entry Headquarter: United States |
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Dynalith Systems Co., Ltd.
CORE COMPETENCY:Acceleration and Emulation, Gate Level Simulation, FPGA/PLD, ESL Co-Verification, ESL Simulation, ESL Test and Verification, RTOS, DSP, Networking, Telecomms, Verification IP, Training and Consulting, Silicon Virtual Prototype, Verilog Simulation, VHDL Simulation, Verification, Acceleration and Emulation, HW/SW Co-Verification, RTL Design and Entry Headquarter: South Korea |
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ClioSoft, Inc.
Empowering Global Collaboration and Design Data Management CORE COMPETENCY:Analog Design, Gate Level/Transistor Level Design, RF Design and Simulation, Schematic Capture, Design Libraries, Enterprise Tools, ASIC Layout, Custom Layout, IC Implementation, Library Development Tools, ESL Design and Entry, Design IP, Verification IP, RTL Design and Entry Headquarter: United States |
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Breker Verification Systems
Predictable Path to 100% Verification Plan Coverage CORE COMPETENCY:DSP, Memory, MEMS, Networking, Telecomms, Wireless, Verification IP, Design Services, Training and Consulting, Verilog Simulation, VHDL Simulation, Verification, Intelligent Test Bench, Mixed Language Simulation Headquarter: United States |
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Bluespec, Inc.
Reinventing Hardware Design(tm) CORE COMPETENCY:ESL Co-Verification, ESL Design and Entry, ESL Logic Synthesis, ESL Power Analysis, ESL Simulation, ESL Test and Verification, Design IP, Verification IP, Design Services, Synthesis, Verification, Acceleration and Emulation, RTL Design and Entry Headquarter: United States |
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Avery Design Systems, Inc.
CORE COMPETENCY:Acceleration and Emulation, Verification IP, Verification, Formal Verification, Intelligent Test Bench Headquarter: United States |
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ARM
THE ARCHITECTURE FOR THE DIGITAL WORLD CORE COMPETENCY:Physical Libraries, Compiler, Debugger, ESL Co-Verification, ESL Design and Entry, ESL Simulation, ESL Test and Verification, Design IP, Verification IP Headquarter: United States |