Variability-robust clock distribution in large-scale ASIC designs!
With scaling technologies, process variations present an increasing hurdle to maintaining timing-safety. With Teklatech's Clock Assembly and Timing tool (the CAT) engineers can effectively address these challenges, bringing modular design all the way to the physical level. Our methods are scalable and technology agnostic and thus track well into sub 65 nm geometries.
The CAT closes the widening gap between logic-level and physical backend, enabling a predictable path to complete SoC integration.
Teklatech features products in the following categories:
- ASIC Layout
- IC Implementation
- Timing Analysis
Diplomvej, bld. 377,
Phone: +45 88 708240