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ESL design is a highly-effective approach for creating complex chips and systems. ESL design has mainstreamed—it is now an established design methodology at most of the world’s leading system-on-chip (SoC) design companies, and it is being used increasingly in system design. To learn more about ESL, read the ESL Design State of the Union 2005 This corner will bring to your attention the latest News, latest products, latest initiative in this field and favor exchange across the IP/SOC community worldwide. Featured IPs: ARM AMBA 2.0 HDL Generator from CoWare Inc. ARM Interconnects TLM SystemC Library from CoWare Inc. ARM Peripherals TLM SystemC Library from CoWare Inc. ARM Processors TLM SystemC Library from CoWare Inc. Broad portfolio of tool-independent transaction-level models (TLMs) for the creation of virtual platforms from Synopsys, Inc. CEVA Processors TLM SystemC Library from CoWare Inc. IBM PPC Processors TLM SystemC Library from CoWare Inc. LSI ZSP Processors TLM SystemC Library from CoWare Inc. More ... Featured EDA Tools: Software models of complete systems that provide software engineers with high-speed, pre-silicon software execution environments that allow the development of SoC-related software before hardware is available from Synopsys, Inc. Powerful, fully integrated tool environment for developing, running and debugging virtual platforms from Synopsys, Inc. VirtualICE from Yokogawa Electric Corporation Virtual Platform Capture and Packaging for Distribution from CoWare, Inc. Virtual Component Co-Design Tools (VCC) from Cadence Design Systems, Inc. Validating Software Earlier, Better, More Reliably from CoWare, Inc. User Retargetable Development Tools from Archelon Inc. unified HW/SW co-verification tool from Adveda More ...

Sponsor Link: Read CoWare's TLM Peripheral Modeling for Platform-Driven ESL Design Using the SystemC Modeling Library White Paper This article provides an overview of a SystemC-based Transaction Level Modeling (TLM) methodology for the rapid creation of SoC platform models. First a brief overview of the ESL design tasks and the corresponding modeling requirements is given. The main topic is a methodology for the efficient creation of transaction-level peripheral models. Those are usually specific for a particular SoC platform and have to be created by the ESL user. Latest News: Imperas Releases Fast Models of PowerPC Processors Through Open Virtual Platforms (OVP) Initiative (Jun. 08, 2010) Calypto's Industry Expands Lead in ESL Verification with Latest SLEC Release (Jun. 07, 2010) Imperas and Open Virtual Platforms (OVP) Initiative Release Full Support for MIPS Technologies' MIPS32 M14K Processors (Apr. 01, 2010) Denali Software and Carbon Team for Transaction-Level Model Distribution (Mar. 24, 2010) Open Virtual Platforms (OVP) Releases Vendor-Verified High Performance Models of Virage Logic's ARC Processors (Mar. 23, 2010) Industry Articles : Embedded system virtualization for executable specifications and use case modeling (Feb. 01, 2010) Virtual testing with model-based design (Aug. 17, 2009) Modelling Embedded Systems at Functional Untimed Application Level (Jun. 25, 2009) Assisted Creation and Refinement of Transactional Level Specifications Based on IP-XACT (May. 18, 2009) Advances in SoC and Processor Modeling Methodologies (Apr. 27, 2009)