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LZR3 Core
Low Latency High-Performance Decompression Core
 

General Description


Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. Lossless compression is used when it is important that the original and the decompressed data be identical, or when no assumption can be made on whether certain deviation is uncritical. Typical applications include data storage and transmission..

LZR3 implements the lossless decompression algorithm on short units of data (“frames”). The core supports configurable maximum frame sizes. The compression algorithm and data formats are the same as in LZR1 and LZR2 cores. Unlike the LZR1 core, LZR3 is designed to have very low latency (few tens of clocks, slightly varies depending on the external interface).

The design is fully synchronous and available in multiple configurations varying in bus widths and throughput.

Symbol

Key Features

  • Each frame is compressed and decompressed independently
  • High throughput: LZR3 easily scales to 10-20 Gbps in FPGA and ASIC
  • Scales in increments of 8 bits per clock (for example, LZR3-4 has a 32-bit interface and has throughput of 32 bits per clock on the decompressed side).
  • Compatibility with public-domain LZ software implementations and LZR1 and LZR2 cores allows for interoperability
  • Decompression–only configuration; other cores or software shall be used for compression.
  • Specified data rate is sustained on the output of the core
  • Configurable decompression window size (default is 4096 bytes)

 

Applications

  • High-performance solid-state storage
 

Pin Description

Name Type Description
CLK Input Core clock signal
RST Input HIGH level asynchronously resets the core
CEN Input Clock enable, bringing this input low pauses the core
START Input Indicates the start of the new frame
Done Output Indicates the end of the frame processing
D[ ] Input Input data bus, width in multiples of 8 bits
Dvalid Input Data on D is valid
Dready Output Core is ready to accept data on D.
len[ ] Input Input data length in bytes
Q[ ] Input Output data bus
Qready Input Core can drive data on Q
Qvalid Output Data on Q is valid
MEM   Memory interface (see the details below)

Function Description


The core implements lossless decompression of blocks of data.

 

Performance

On the Calgary corpus with the 4096-byte block the core exhibits the following performance:

File Compression ratio File Compression Ratio
bib 1.56 (64.2%)
paper3
1.49 (66.9%)
book1 1.39 (72.0%)
paper4
1.54 (64.8%)
book2 1.58 (63.1%)
paper5
1.59 (63.0%)

geo

1.13 (88.5%)
paper6
1.64 (60.9%)
news 1.51 (66.0%)
pic
4.08 (24.5%)
obj1 1.60 (62.7%)
progc
1.74 (57.6%)
obj2 1.83 (54.5%)
progl
2.13 (46.8%)
paper1 1.61 (62.0%)
progp
2.13 (47.0%)
paper2 1.54 (65.1%)
trans
1.93 (51.7%)

 

 

 

 

 

 

 

 

On the Canterbury corpus with the 4096-byte block the core exhibits the following performance:

File Compression ratio File Compression Ratio
alice29.txt 1.54 (65.10%)
sum
1.70 (58.84%)
asyoulik.txt 1.48 (67.40%)
xargs.1
1.77 (56.38%)
cp.html 1.76 (56.86%)
lcet10.txt
1.57 (63.69%)

fields.c

2.13 (46.85%)
plrabn12.txt
1.40 (71.28%)
grammar.lsp 2.10 (47.68%)
ptt5
4.08 (24.52%)
kennedy.xls 3.11 (32.16%)
 

 

 

 

Synthesis results

Configuration with 4096 bytes block


  LZR3-4, 16 Gbps @ 500 MHz LZR3-8, 16 Gbps @ 250 MHz
Gates
Memories 4096x8 bits each Two-port (R+W)
Gates
Memories 4096x8 bits each Two-port (R+W)
Configuration with RAM
35K
4
60K
8
Configuration w/o RAM
380K
-
590K
-