Traditional Cost Reduction Returns At 10nm, says Globalfoundries.

Although there will not be the normal Moore’s Law 30% transistor cost reduction at 20nm, Globalfoundries reckons the successor node – 10nm – will see a return to the traditional cost curve“The cost is going up but there are technology optimisations that can be implemented, ”
Subi Kengeri vice president for advanced technology architecture, told the Globalfoundries EMEA Technical Seminar in London on Monday.

The extra cost of double patterning means that, at the 20nm node, the cost reduction will not be as much as the traditional 30%.

For Globalfoundries this interruption in the traditional pace of cost reduction will only be a one node blip, reckons Kengeri.

“Even without EUV we will get back to the traditional Moore’s Law cost reduction curve at 10nm because of process optimisations,” said Kengeri.

Last week TSMC’s senior director for R&D, Yee-Chaung See, suggested to IEF2013 that the prospective cost of a 10nm wafer could be 4x the cost of a 28nm wafer and said “many innovations” are needed to bring the cost down.

250W light source EUV would solve everything but the highest power light source available now is 15W.

Kengeri reckons that EUV will come in at 7nm because there won’t be any other way of doing the litho.