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As the latest addition to the Rambus portfolio of industry-leading interface and security digital IP for AI 2.0, the GDDR7 memory controller will provide ... Read
RAAAM Memory Technologies Closes $4M Seed Round to Commercialize Super Cost Effective On-Chip ...
RAAAM Memory Technologies, a start-up company that invented a groundbreaking solution to implement on-chip memory, announced today that it has completed ... Read
QUALITAS SEMICONDUCTOR CO., LTD. (QUALITAS) (KOSDAQ: 432720), a leading provider of interconnect solutions, proudly announces the appointment of HongKong ... Read
Partner Highlight
Silicon Creations, a leading supplier of high-performance analog and mixed-signal intellectual property (IP), announced a significant milestone: surpassing ... Read
Omni Design Technologies, a leading provider of high-performance, low-power mixed-signal intellectual property (IP), today announced it has joined the ... Read
Global Unichip Corp. (GUC), the Advanced ASIC Leader, announced today that the GLink-3D interface (GUC’s Link for 3D die stacking) for the TSMC 3DFabric ... Read
Industry Expert Blogs
Cadence Blog Anika Sunda, Cadence
SemiWiki Eric Esteve, IPnest
arm Blogs Tim Thornton, Arm
Ceva's Experts blog By Tomer Yablonka, Ceva
32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 ...
High-performance mixed-precision NPU IP
ASIL B Ready PCIe 5.0 Integrity and Data Encryption (IDE) Security ...
DVB-S2X Wideband LDPC BCH Decoder
Aeonic Generate™ AWM3
3.3V general purpose I/O for 28nm CMOS
One Time Programmable IP on Samsung 90CIS
112Gbps VSR to extended LR SerDes IP on TSMC N7/N6
Fast Fourier Transform IP Core
ETHOS-U85 NPU
APXM-6200 - 64-bit, highly efficient application RISC-V CPU
Crypto Module IP core
Multi-protocol wireless plaform integrating 802.11ax (Wi-Fi ...
BoW Verification IP
USB4 v2.0 Verification IP
Simulation VIP for MIPI SoundWire-I3S
MIPI A-PHY Verification IP
UCIe Verification IP
Synthesizable DDR5 Bus Functional Model
SGPIO Verification IP
USB-C 3.1 DP/TX PHY ebdaux in TSMC (N5, N3E)
Industry Articles
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From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs
Vincenzo Liguori
Ocean Logic -
Embracing a More Secure Era with TLS 1.3
Lawrence Liu
PUFsecurity -
New PCIe Gen6 CXL3.0 retimer: a small chip for big next-gen AI
Anton Shilov
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Maximizing ESD protection for automotive Ethernet applications
Andreas Hardock
Nexperia -
The role of cache in AI processor design
Frank Schirrmeister
Arteris -
Time Sensitive Networking for Aerospace
CAST and Fraunhofer IPMS
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Understanding mmWave RADAR, its Principle & Applications
Snehal Buche
eInfochips -
Advanced Topics in FinFET Back-End Layout, Analog Techniques, and Design Tools
AsicNorth
